Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7808960	1			T1	8188		T2	75183		T3	1
all_pins[1]	7808960	1			T1	8188		T2	75183		T3	1
all_pins[2]	7808960	1			T1	8188		T2	75183		T3	1
all_pins[3]	7808960	1			T1	8188		T2	75183		T3	1
all_pins[4]	7808960	1			T1	8188		T2	75183		T3	1
all_pins[5]	7808960	1			T1	8188		T2	75183		T3	1
all_pins[6]	7808960	1			T1	8188		T2	75183		T3	1
all_pins[7]	7808960	1			T1	8188		T2	75183		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	62249751	1			T1	65504		T2	601464		T3	8
values[0x1]	221929	1			T28	15		T31	17		T69	8
transitions[0x0=>0x1]	217089	1			T28	13		T31	14		T69	7
transitions[0x1=>0x0]	217106	1			T28	14		T31	14		T69	7

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7807082	1			T1	8188		T2	75183		T3	1
all_pins[0]	values[0x1]	1878	1			T28	2		T31	1		T68	4
all_pins[0]	transitions[0x0=>0x1]	1567	1			T28	2		T31	1		T68	4
all_pins[0]	transitions[0x1=>0x0]	575	1			T69	1		T70	1		T154	3
all_pins[1]	values[0x0]	7808074	1			T1	8188		T2	75183		T3	1
all_pins[1]	values[0x1]	886	1			T69	1		T70	1		T154	5
all_pins[1]	transitions[0x0=>0x1]	612	1			T70	1		T154	3		T155	1
all_pins[1]	transitions[0x1=>0x0]	300	1			T28	2		T31	3		T68	2
all_pins[2]	values[0x0]	7808386	1			T1	8188		T2	75183		T3	1
all_pins[2]	values[0x1]	574	1			T28	2		T31	3		T69	1
all_pins[2]	transitions[0x0=>0x1]	512	1			T28	1		T31	3		T69	1
all_pins[2]	transitions[0x1=>0x0]	114	1			T28	2		T69	2		T154	6
all_pins[3]	values[0x0]	7808784	1			T1	8188		T2	75183		T3	1
all_pins[3]	values[0x1]	176	1			T28	3		T69	2		T68	2
all_pins[3]	transitions[0x0=>0x1]	144	1			T28	3		T69	2		T68	1
all_pins[3]	transitions[0x1=>0x0]	150	1			T31	4		T69	1		T154	3
all_pins[4]	values[0x0]	7808778	1			T1	8188		T2	75183		T3	1
all_pins[4]	values[0x1]	182	1			T31	4		T69	1		T68	1
all_pins[4]	transitions[0x0=>0x1]	146	1			T31	2		T69	1		T68	1
all_pins[4]	transitions[0x1=>0x0]	6333	1			T28	2		T31	1		T69	2
all_pins[5]	values[0x0]	7802591	1			T1	8188		T2	75183		T3	1
all_pins[5]	values[0x1]	6369	1			T28	2		T31	3		T69	2
all_pins[5]	transitions[0x0=>0x1]	2366	1			T28	2		T31	3		T69	2
all_pins[5]	transitions[0x1=>0x0]	207671	1			T28	1		T69	1		T70	3
all_pins[6]	values[0x0]	7597286	1			T1	8188		T2	75183		T3	1
all_pins[6]	values[0x1]	211674	1			T28	1		T69	1		T70	3
all_pins[6]	transitions[0x0=>0x1]	211616	1			T28	1		T69	1		T70	2
all_pins[6]	transitions[0x1=>0x0]	132	1			T28	5		T31	6		T68	1
all_pins[7]	values[0x0]	7808770	1			T1	8188		T2	75183		T3	1
all_pins[7]	values[0x1]	190	1			T28	5		T31	6		T70	1
all_pins[7]	transitions[0x0=>0x1]	126	1			T28	4		T31	5		T70	1
all_pins[7]	transitions[0x1=>0x0]	1831	1			T28	2		T68	4		T154	8