Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 0 18 100.00
Crosses 128 1 127 99.22


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_data 8 0 8 100.00 100 1 1 0
cp_mask 8 0 8 100.00 100 1 1 0
cp_payload_swap_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 1 127 99.22 100 1 1 0


Summary for Variable cp_data

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_data

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4352 1 T1 20 T2 48 T6 18
values[1] 3532 1 T2 22 T23 178 T169 4
values[2] 4631 1 T1 124 T2 44 T13 43
values[3] 4520 1 T1 60 T2 27 T13 23
values[4] 4550 1 T1 120 T23 96 T162 20
values[5] 4178 1 T1 149 T10 12 T23 49
values[6] 3873 1 T1 20 T5 8 T107 10
values[7] 5200 1 T11 22 T23 252 T170 10



Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4033 1 T1 20 T2 45 T12 12
values[1] 4073 1 T1 273 T5 8 T10 12
values[2] 5121 1 T1 20 T2 20 T13 31
values[3] 4805 1 T1 40 T23 219 T27 24
values[4] 4254 1 T6 18 T23 49 T162 20
values[5] 4368 1 T1 20 T2 76 T11 22
values[6] 4400 1 T1 120 T23 130 T171 8
values[7] 3782 1 T8 30 T145 34 T23 20



Summary for Variable cp_payload_swap_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_payload_swap_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34311 1 T1 483 T2 134 T5 8
auto[1] 525 1 T1 10 T2 7 T13 2



Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 1 127 99.22 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_payload_swap_encp_datacp_maskCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [values[5]] [values[2]] 0 1 1


Covered bins
cp_payload_swap_encp_datacp_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] values[0] 728 1 T1 20 T12 12 T23 20
auto[0] values[0] values[1] 431 1 T88 26 T31 20 T53 10
auto[0] values[0] values[2] 452 1 T2 20 T13 31 T172 2
auto[0] values[0] values[3] 539 1 T23 35 T173 10 T70 32
auto[0] values[0] values[4] 625 1 T6 18 T34 20 T70 80
auto[0] values[0] values[5] 490 1 T2 25 T88 51 T174 56
auto[0] values[0] values[6] 439 1 T164 39 T175 20 T20 20
auto[0] values[0] values[7] 586 1 T8 30 T88 20 T31 39
auto[0] values[1] values[0] 342 1 T2 22 T23 63 T28 17
auto[0] values[1] values[1] 418 1 T32 26 T20 20 T176 20
auto[0] values[1] values[2] 504 1 T177 2 T174 20 T178 41
auto[0] values[1] values[3] 427 1 T23 61 T32 23 T136 20
auto[0] values[1] values[4] 377 1 T179 20 T180 19 T21 20
auto[0] values[1] values[5] 553 1 T28 73 T31 28 T83 4
auto[0] values[1] values[6] 612 1 T23 53 T169 4 T181 8
auto[0] values[1] values[7] 240 1 T28 40 T31 43 T84 28
auto[0] values[2] values[0] 681 1 T2 23 T13 43 T88 42
auto[0] values[2] values[1] 436 1 T1 119 T35 14 T31 20
auto[0] values[2] values[2] 852 1 T31 46 T70 40 T182 10
auto[0] values[2] values[3] 717 1 T23 81 T165 28 T183 18
auto[0] values[2] values[4] 384 1 T163 4 T28 20 T174 20
auto[0] values[2] values[5] 473 1 T2 19 T184 20 T23 61
auto[0] values[2] values[6] 592 1 T23 20 T70 46 T178 47
auto[0] values[2] values[7] 425 1 T145 34 T185 74 T186 27
auto[0] values[3] values[0] 366 1 T85 12 T32 39 T187 24
auto[0] values[3] values[1] 592 1 T188 12 T179 25 T189 28
auto[0] values[3] values[2] 732 1 T29 26 T34 31 T70 19
auto[0] values[3] values[3] 669 1 T1 40 T23 20 T27 24
auto[0] values[3] values[4] 449 1 T23 23 T174 20 T57 2
auto[0] values[3] values[5] 543 1 T1 20 T2 25 T13 21
auto[0] values[3] values[6] 509 1 T171 8 T139 23 T190 47
auto[0] values[3] values[7] 595 1 T88 21 T31 20 T174 25
auto[0] values[4] values[0] 728 1 T23 20 T178 99 T20 22
auto[0] values[4] values[1] 351 1 T23 20 T88 26 T32 20
auto[0] values[4] values[2] 897 1 T34 20 T70 20 T178 19
auto[0] values[4] values[3] 643 1 T20 20 T191 2 T190 29
auto[0] values[4] values[4] 504 1 T162 20 T192 25 T193 33
auto[0] values[4] values[5] 460 1 T32 19 T194 20 T34 48
auto[0] values[4] values[6] 539 1 T1 118 T23 55 T195 4
auto[0] values[4] values[7] 356 1 T34 43 T196 21 T197 25
auto[0] values[5] values[0] 317 1 T198 4 T199 20 T20 25
auto[0] values[5] values[1] 728 1 T1 146 T10 12 T32 21
auto[0] values[5] values[2] 173 1 T174 20 T200 6 T201 20
auto[0] values[5] values[3] 577 1 T28 40 T31 20 T174 20
auto[0] values[5] values[4] 583 1 T23 26 T28 113 T32 20
auto[0] values[5] values[5] 397 1 T23 22 T202 10 T88 20
auto[0] values[5] values[6] 690 1 T136 27 T203 2 T196 20
auto[0] values[5] values[7] 655 1 T178 75 T138 19 T176 23
auto[0] values[6] values[0] 408 1 T86 14 T88 20 T204 4
auto[0] values[6] values[1] 478 1 T5 8 T28 38 T205 6
auto[0] values[6] values[2] 647 1 T1 20 T174 37 T178 113
auto[0] values[6] values[3] 581 1 T28 63 T164 35 T31 23
auto[0] values[6] values[4] 566 1 T31 20 T178 107 T190 22
auto[0] values[6] values[5] 314 1 T30 10 T20 22 T190 20
auto[0] values[6] values[6] 365 1 T206 16 T70 58 T207 26
auto[0] values[6] values[7] 461 1 T107 10 T31 41 T174 72
auto[0] values[7] values[0] 398 1 T170 10 T31 23 T34 21
auto[0] values[7] values[1] 570 1 T23 38 T208 26 T174 20
auto[0] values[7] values[2] 787 1 T32 25 T174 117 T209 10
auto[0] values[7] values[3] 598 1 T23 19 T32 41 T34 20
auto[0] values[7] values[4] 711 1 T210 6 T31 20 T34 66
auto[0] values[7] values[5] 1069 1 T11 22 T23 170 T211 127
auto[0] values[7] values[6] 589 1 T212 36 T88 22 T164 53
auto[0] values[7] values[7] 393 1 T23 20 T213 4 T28 55
auto[1] values[0] values[0] 5 1 T21 1 T214 1 T215 3
auto[1] values[0] values[1] 9 1 T139 3 T216 3 T217 1
auto[1] values[0] values[2] 8 1 T33 4 T174 2 T138 1
auto[1] values[0] values[3] 11 1 T23 1 T158 3 T159 4
auto[1] values[0] values[4] 4 1 T70 1 T179 1 T218 1
auto[1] values[0] values[5] 12 1 T2 3 T88 3 T176 2
auto[1] values[0] values[6] 4 1 T139 2 T219 2 - -
auto[1] values[0] values[7] 9 1 T31 1 T20 2 T186 2
auto[1] values[1] values[0] 9 1 T28 3 T31 1 T220 2
auto[1] values[1] values[1] 6 1 T32 2 T216 1 T217 1
auto[1] values[1] values[2] 9 1 T186 1 T219 2 T221 3
auto[1] values[1] values[3] 4 1 T32 2 T222 2 - -
auto[1] values[1] values[4] 8 1 T180 1 T223 2 T159 2
auto[1] values[1] values[5] 9 1 T31 2 T34 1 T224 3
auto[1] values[1] values[6] 7 1 T23 1 T201 2 T221 1
auto[1] values[1] values[7] 7 1 T31 2 T225 1 T186 1
auto[1] values[2] values[0] 6 1 T220 1 T226 2 T227 1
auto[1] values[2] values[1] 14 1 T1 5 T190 1 T47 3
auto[1] values[2] values[2] 19 1 T31 3 T179 1 T228 4
auto[1] values[2] values[3] 6 1 T23 1 T138 1 T196 1
auto[1] values[2] values[4] 3 1 T20 1 T197 1 T21 1
auto[1] values[2] values[5] 9 1 T2 2 T23 1 T136 4
auto[1] values[2] values[6] 9 1 T192 1 T21 2 T201 3
auto[1] values[2] values[7] 5 1 T185 1 T186 1 T201 2
auto[1] values[3] values[0] 7 1 T229 2 T230 1 T231 4
auto[1] values[3] values[1] 6 1 T189 2 T224 1 T158 1
auto[1] values[3] values[2] 8 1 T70 1 T193 1 T219 1
auto[1] values[3] values[3] 8 1 T196 1 T21 2 T193 1
auto[1] values[3] values[4] 1 1 T193 1 - - - -
auto[1] values[3] values[5] 11 1 T2 2 T13 2 T228 1
auto[1] values[3] values[6] 8 1 T190 2 T228 1 T232 1
auto[1] values[3] values[7] 16 1 T174 1 T196 1 T185 2
auto[1] values[4] values[0] 16 1 T178 1 T20 1 T176 1
auto[1] values[4] values[1] 2 1 T138 2 - - - -
auto[1] values[4] values[2] 16 1 T178 1 T225 2 T185 2
auto[1] values[4] values[3] 10 1 T180 1 T201 2 T233 1
auto[1] values[4] values[4] 9 1 T193 2 T233 4 T232 1
auto[1] values[4] values[5] 4 1 T32 1 T34 2 T234 1
auto[1] values[4] values[6] 9 1 T1 2 T23 1 T186 2
auto[1] values[4] values[7] 6 1 T196 1 T197 3 T217 1
auto[1] values[5] values[0] 3 1 T20 1 T226 1 T96 1
auto[1] values[5] values[1] 13 1 T1 3 T32 2 T174 1
auto[1] values[5] values[3] 2 1 T235 1 T236 1 - -
auto[1] values[5] values[4] 13 1 T28 1 T70 2 T178 2
auto[1] values[5] values[5] 9 1 T23 1 T178 2 T190 1
auto[1] values[5] values[6] 8 1 T192 1 T47 1 T223 1
auto[1] values[5] values[7] 10 1 T138 1 T176 1 T232 1
auto[1] values[6] values[0] 5 1 T233 1 T226 2 T237 2
auto[1] values[6] values[1] 6 1 T28 3 T234 1 T221 2
auto[1] values[6] values[2] 5 1 T174 1 T192 2 T238 2
auto[1] values[6] values[3] 4 1 T20 1 T197 2 T239 1
auto[1] values[6] values[4] 9 1 T31 1 T178 2 T190 1
auto[1] values[6] values[5] 5 1 T30 2 T225 1 T230 1
auto[1] values[6] values[6] 8 1 T70 3 T196 1 T223 2
auto[1] values[6] values[7] 11 1 T31 1 T174 3 T178 3
auto[1] values[7] values[0] 14 1 T31 3 T178 2 T240 1
auto[1] values[7] values[1] 13 1 T23 2 T20 2 T228 2
auto[1] values[7] values[2] 12 1 T32 1 T174 4 T185 2
auto[1] values[7] values[3] 9 1 T23 1 T192 1 T220 3
auto[1] values[7] values[4] 8 1 T70 2 T96 2 T241 1
auto[1] values[7] values[5] 10 1 T23 2 T242 1 T243 2
auto[1] values[7] values[6] 12 1 T164 3 T224 3 T201 1
auto[1] values[7] values[7] 7 1 T225 1 T192 2 T47 1

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