Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2519

1

T2

9

T3

22

T13

4

auto[1]

2534

1

T2

12

T3

20

T13

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2724

1

T2

21

T13

7

T15

4

auto[1]

2329

1

T3

42

T14

3

T15

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4014

1

T2

13

T3

42

T13

6

auto[1]

1039

1

T2

8

T13

1

T15

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1041	1			T2	2		T3	9		T13	1
valid[1]	973	1			T2	4		T3	11		T13	4
valid[2]	1060	1			T2	4		T3	8		T13	1
valid[3]	1034	1			T2	5		T3	5		T14	1
valid[4]	945	1			T2	6		T3	9		T13	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	190	1			T2	2		T13	1		T25	3
auto[0]	auto[0]	valid[0]	auto[1]	243	1			T3	6		T15	1		T16	6
auto[0]	auto[0]	valid[1]	auto[0]	178	1			T2	1		T13	3		T25	1
auto[0]	auto[0]	valid[1]	auto[1]	206	1			T3	5		T15	1		T16	2
auto[0]	auto[0]	valid[2]	auto[0]	190	1			T2	1		T15	1		T25	1
auto[0]	auto[0]	valid[2]	auto[1]	235	1			T3	3		T16	8		T39	4
auto[0]	auto[0]	valid[3]	auto[0]	158	1			T2	2		T25	1		T95	1
auto[0]	auto[0]	valid[3]	auto[1]	244	1			T3	3		T14	1		T16	3
auto[0]	auto[0]	valid[4]	auto[0]	149	1			T2	1		T25	1		T44	2
auto[0]	auto[0]	valid[4]	auto[1]	224	1			T3	5		T14	1		T16	5
auto[0]	auto[1]	valid[0]	auto[0]	161	1			T25	2		T44	1		T95	1
auto[0]	auto[1]	valid[0]	auto[1]	233	1			T3	3		T16	1		T39	7
auto[0]	auto[1]	valid[1]	auto[0]	166	1			T2	2		T13	1		T41	1
auto[0]	auto[1]	valid[1]	auto[1]	218	1			T3	6		T16	9		T39	2
auto[0]	auto[1]	valid[2]	auto[0]	170	1			T15	1		T25	2		T41	2
auto[0]	auto[1]	valid[2]	auto[1]	244	1			T3	5		T16	6		T39	2
auto[0]	auto[1]	valid[3]	auto[0]	165	1			T2	1		T25	2		T93	2
auto[0]	auto[1]	valid[3]	auto[1]	260	1			T3	2		T16	8		T39	3
auto[0]	auto[1]	valid[4]	auto[0]	158	1			T2	3		T13	1		T25	2
auto[0]	auto[1]	valid[4]	auto[1]	222	1			T3	4		T14	1		T16	3
auto[1]	auto[0]	valid[0]	auto[0]	103	1			T25	1		T94	1		T88	1
auto[1]	auto[0]	valid[1]	auto[0]	93	1			T43	1		T244	1		T94	1
auto[1]	auto[0]	valid[2]	auto[0]	106	1			T2	1		T25	1		T41	1
auto[1]	auto[0]	valid[3]	auto[0]	107	1			T15	1		T25	1		T95	1
auto[1]	auto[0]	valid[4]	auto[0]	93	1			T2	1		T25	1		T43	1
auto[1]	auto[1]	valid[0]	auto[0]	111	1			T43	2		T94	1		T88	1
auto[1]	auto[1]	valid[1]	auto[0]	112	1			T2	1		T95	2		T254	1
auto[1]	auto[1]	valid[2]	auto[0]	115	1			T2	2		T13	1		T94	1
auto[1]	auto[1]	valid[3]	auto[0]	100	1			T2	2		T15	1		T93	1
auto[1]	auto[1]	valid[4]	auto[0]	99	1			T2	1		T25	1		T41	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal