Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67611

1

T2

421

T13

71

T15

173

auto[1]

25399

1

T3

430

T13

30

T14

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68402

1

T2

287

T3

430

T13

71

auto[1]

24608

1

T2

134

T13

30

T15

66

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	47841	1			T2	218		T3	212		T13	58
others[1]	7853	1			T2	48		T3	37		T13	9
others[2]	7828	1			T2	28		T3	35		T13	10
others[3]	8930	1			T2	42		T3	50		T13	8
interest[1]	5274	1			T2	21		T3	29		T13	3
interest[4]	31313	1			T2	143		T3	141		T13	37
interest[64]	15284	1			T2	64		T3	67		T13	13

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	22171	1			T2	154		T13	26		T15	59
auto[0]	auto[0]	others[1]	3620	1			T2	32		T13	2		T15	7
auto[0]	auto[0]	others[2]	3684	1			T2	19		T13	3		T15	5
auto[0]	auto[0]	others[3]	4053	1			T2	27		T13	2		T15	12
auto[0]	auto[0]	interest[1]	2409	1			T2	16		T13	1		T15	8
auto[0]	auto[0]	interest[4]	14360	1			T2	103		T13	16		T15	37
auto[0]	auto[0]	interest[64]	7066	1			T2	39		T13	7		T15	16
auto[0]	auto[1]	others[0]	13179	1			T3	212		T13	12		T14	3
auto[0]	auto[1]	others[1]	2129	1			T3	37		T13	3		T15	2
auto[0]	auto[1]	others[2]	2055	1			T3	35		T13	5		T15	3
auto[0]	auto[1]	others[3]	2509	1			T3	50		T13	4		T15	1
auto[0]	auto[1]	interest[1]	1429	1			T3	29		T13	1		T15	1
auto[0]	auto[1]	interest[4]	8747	1			T3	141		T13	8		T14	3
auto[0]	auto[1]	interest[64]	4098	1			T3	67		T13	5		T15	1
auto[1]	auto[0]	others[0]	12491	1			T2	64		T13	20		T15	34
auto[1]	auto[0]	others[1]	2104	1			T2	16		T13	4		T15	4
auto[1]	auto[0]	others[2]	2089	1			T2	9		T13	2		T15	2
auto[1]	auto[0]	others[3]	2368	1			T2	15		T13	2		T15	13
auto[1]	auto[0]	interest[1]	1436	1			T2	5		T13	1		T15	2
auto[1]	auto[0]	interest[4]	8206	1			T2	40		T13	13		T15	24
auto[1]	auto[0]	interest[64]	4120	1			T2	25		T13	1		T15	11

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal