Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	851	1			T28	11		T31	7		T69	4
all_values[1]	851	1			T28	11		T31	7		T69	4
all_values[2]	851	1			T28	11		T31	7		T69	4
all_values[3]	851	1			T28	11		T31	7		T69	4
all_values[4]	851	1			T28	11		T31	7		T69	4
all_values[5]	851	1			T28	11		T31	7		T69	4
all_values[6]	851	1			T28	11		T31	7		T69	4
all_values[7]	851	1			T28	11		T31	7		T69	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3614

1

T28

47

T31

27

T69

16

auto[1]

3194

1

T28

41

T31

29

T69

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2814

1

T28

49

T31

26

T69

13

auto[1]

3994

1

T28

39

T31

30

T69

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3938

1

T28

59

T31

32

T69

19

auto[1]

2870

1

T28

29

T31

24

T69

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	168	1			T28	3		T31	2		T69	1
all_values[0]	auto[0]	auto[0]	auto[1]	105	1			T28	1		T69	2		T68	1
all_values[0]	auto[0]	auto[1]	auto[0]	157	1			T28	3		T31	1		T70	1
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T28	1		T68	2		T154	3
all_values[0]	auto[1]	auto[0]	auto[1]	187	1			T28	2		T31	2		T69	1
all_values[0]	auto[1]	auto[1]	auto[1]	162	1			T28	1		T31	2		T68	3
all_values[1]	auto[0]	auto[0]	auto[0]	179	1			T28	7		T31	2		T154	8
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T31	1		T70	2		T68	2
all_values[1]	auto[0]	auto[1]	auto[0]	168	1			T28	4		T31	3		T69	2
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T70	1		T154	2		T156	2
all_values[1]	auto[1]	auto[0]	auto[1]	181	1			T31	1		T69	1		T70	1
all_values[1]	auto[1]	auto[1]	auto[1]	171	1			T69	1		T68	1		T154	4
all_values[2]	auto[0]	auto[0]	auto[0]	159	1			T28	5		T31	1		T69	1
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T28	1		T69	1		T70	1
all_values[2]	auto[0]	auto[1]	auto[0]	128	1			T28	1		T31	1		T154	4
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T28	1		T31	1		T154	3
all_values[2]	auto[1]	auto[0]	auto[1]	211	1			T28	2		T31	2		T70	1
all_values[2]	auto[1]	auto[1]	auto[1]	180	1			T28	1		T31	2		T69	2
all_values[3]	auto[0]	auto[0]	auto[0]	196	1			T28	2		T31	2		T70	1
all_values[3]	auto[0]	auto[0]	auto[1]	66	1			T70	1		T68	1		T154	5
all_values[3]	auto[0]	auto[1]	auto[0]	151	1			T28	3		T31	3		T70	1
all_values[3]	auto[0]	auto[1]	auto[1]	83	1			T28	1		T69	1		T68	1
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T28	1		T31	2		T69	1
all_values[3]	auto[1]	auto[1]	auto[1]	173	1			T28	4		T69	2		T68	2
all_values[4]	auto[0]	auto[0]	auto[0]	170	1			T28	2		T69	1		T70	2
all_values[4]	auto[0]	auto[0]	auto[1]	89	1			T69	1		T70	1		T68	2
all_values[4]	auto[0]	auto[1]	auto[0]	171	1			T28	7		T31	2		T69	1
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T31	1		T154	1		T155	2
all_values[4]	auto[1]	auto[0]	auto[1]	190	1			T28	1		T31	1		T70	1
all_values[4]	auto[1]	auto[1]	auto[1]	165	1			T28	1		T31	3		T69	1
all_values[5]	auto[0]	auto[0]	auto[0]	294	1			T28	4		T31	1		T69	1
all_values[5]	auto[0]	auto[1]	auto[0]	214	1			T28	2		T31	3		T69	1
all_values[5]	auto[1]	auto[0]	auto[1]	179	1			T28	3		T31	2		T70	2
all_values[5]	auto[1]	auto[1]	auto[1]	164	1			T28	2		T31	1		T69	2
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T31	4		T69	1		T68	1
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T28	4		T68	2		T154	3
all_values[6]	auto[0]	auto[1]	auto[0]	151	1			T28	1		T31	1		T69	1
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T69	1		T70	1		T68	1
all_values[6]	auto[1]	auto[0]	auto[1]	185	1			T28	4		T31	1		T154	7
all_values[6]	auto[1]	auto[1]	auto[1]	182	1			T28	2		T31	1		T69	1
all_values[7]	auto[0]	auto[0]	auto[0]	192	1			T28	4		T69	3		T68	3
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T31	1		T70	1		T154	3
all_values[7]	auto[0]	auto[1]	auto[0]	142	1			T28	1		T68	1		T154	4
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T28	1		T31	2		T154	3
all_values[7]	auto[1]	auto[0]	auto[1]	191	1			T28	1		T31	2		T69	1
all_values[7]	auto[1]	auto[1]	auto[1]	167	1			T28	4		T31	2		T70	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal