Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	9410364	1			T1	6167		T2	6865		T3	4095
all_values[1]	9410364	1			T1	6167		T2	6865		T3	4095
all_values[2]	9410364	1			T1	6167		T2	6865		T3	4095
all_values[3]	9410364	1			T1	6167		T2	6865		T3	4095
all_values[4]	9410364	1			T1	6167		T2	6865		T3	4095
all_values[5]	9410364	1			T1	6167		T2	6865		T3	4095
all_values[6]	9410364	1			T1	6167		T2	6865		T3	4095
all_values[7]	9410364	1			T1	6167		T2	6865		T3	4095

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73150499

1

T1

49336

T2

54920

T3

32760

auto[1]

2132413

1

T26

108

T19

210266

T59

53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75189482

1

T1

49171

T2

54920

T3

32760

auto[1]

93430

1

T1

165

T8

354

T10

213

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	9116880	1			T1	6060		T2	6865		T3	4095
all_values[0]	auto[0]	auto[1]	51138	1			T1	107		T8	221		T10	102
all_values[0]	auto[1]	auto[0]	240287	1			T26	4		T59	2		T60	1
all_values[0]	auto[1]	auto[1]	2059	1			T26	7		T59	2		T60	2
all_values[1]	auto[0]	auto[0]	9276487	1			T1	6132		T2	6865		T3	4095
all_values[1]	auto[0]	auto[1]	26987	1			T1	35		T8	127		T10	76
all_values[1]	auto[1]	auto[0]	106416	1			T26	3		T19	1		T59	8
all_values[1]	auto[1]	auto[1]	474	1			T26	6		T19	1		T59	1
all_values[2]	auto[0]	auto[0]	9361162	1			T1	6144		T2	6865		T3	4095
all_values[2]	auto[0]	auto[1]	10344	1			T1	23		T8	6		T10	35
all_values[2]	auto[1]	auto[0]	38594	1			T26	11		T59	4		T60	3
all_values[2]	auto[1]	auto[1]	264	1			T26	6		T19	1		T59	3
all_values[3]	auto[0]	auto[0]	9209294	1			T1	6167		T2	6865		T3	4095
all_values[3]	auto[0]	auto[1]	218	1			T26	3		T59	3		T123	1
all_values[3]	auto[1]	auto[0]	200644	1			T26	7		T19	70084		T59	4
all_values[3]	auto[1]	auto[1]	208	1			T26	6		T19	3		T59	5
all_values[4]	auto[0]	auto[0]	9028673	1			T1	6167		T2	6865		T3	4095
all_values[4]	auto[0]	auto[1]	193	1			T26	5		T59	3		T60	4
all_values[4]	auto[1]	auto[0]	381301	1			T26	8		T19	70084		T59	3
all_values[4]	auto[1]	auto[1]	197	1			T26	2		T19	3		T59	4
all_values[5]	auto[0]	auto[0]	9054849	1			T1	6167		T2	6865		T3	4095
all_values[5]	auto[0]	auto[1]	406	1			T13	3		T26	3		T19	1
all_values[5]	auto[1]	auto[0]	354944	1			T26	4		T59	3		T60	2
all_values[5]	auto[1]	auto[1]	165	1			T26	4		T59	1		T60	2
all_values[6]	auto[0]	auto[0]	9035448	1			T1	6167		T2	6865		T3	4095
all_values[6]	auto[0]	auto[1]	202	1			T26	2		T59	1		T60	4
all_values[6]	auto[1]	auto[0]	374514	1			T26	7		T19	2		T59	3
all_values[6]	auto[1]	auto[1]	200	1			T26	12		T59	2		T60	2
all_values[7]	auto[0]	auto[0]	8978051	1			T1	6167		T2	6865		T3	4095
all_values[7]	auto[0]	auto[1]	167	1			T26	1		T59	3		T60	3
all_values[7]	auto[1]	auto[0]	431938	1			T26	13		T19	70084		T59	2
all_values[7]	auto[1]	auto[1]	208	1			T26	8		T19	3		T59	6