Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	44223	1			T1	136		T7	4		T8	226
auto[SpiFlashAddrCfg]	9992	1			T1	46		T3	8		T4	2
auto[SpiFlashAddr3b]	12429	1			T1	57		T3	8		T4	4
auto[SpiFlashAddr4b]	9943	1			T1	48		T4	2		T8	12

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44738

1

T1

189

T3

16

T4

8

auto[1]

31849

1

T1

98

T6

2

T8

141

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40958

1

T1

174

T3

6

T4

6

auto[1]

35629

1

T1

113

T3

10

T4

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	50410	1			T1	155		T7	4		T8	248
values[1]	1475	1			T1	8		T10	9		T11	6
values[2]	1887	1			T1	5		T8	1		T10	5
values[3]	1932	1			T1	8		T6	2		T8	4
values[4]	1857	1			T1	7		T8	2		T10	8
values[5]	2034	1			T1	10		T3	8		T8	4
values[6]	2012	1			T1	20		T8	2		T10	9
values[7]	1903	1			T1	8		T4	2		T8	4
values[8]	13077	1			T1	66		T3	8		T4	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37493

1

T1

179

T4

8

T6

2

auto[1]

39094

1

T1

108

T3

16

T8

274

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

73662

1

T1

276

T3

16

T4

8

write

2925

1

T1

11

T8

10

T10

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

26340

1

T1

117

T3

16

T4

4

valids[0x1]

50247

1

T1

170

T4

4

T7

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	2135	1			T1	7		T8	3		T9	4
internal_process_ops[0x5a]	2094	1			T1	14		T8	3		T9	2
internal_process_ops[0x05]	25679	1			T1	58		T7	2		T8	195
internal_process_ops[0x35]	2108	1			T1	13		T8	5		T9	2
internal_process_ops[0x15]	1999	1			T1	9		T7	2		T8	1
internal_process_ops[0x03]	1424	1			T1	8		T10	5		T11	5
internal_process_ops[0x0b]	1360	1			T1	9		T4	4		T8	1
internal_process_ops[0x3b]	1553	1			T1	7		T3	6		T10	9
internal_process_ops[0x6b]	1421	1			T1	7		T3	2		T4	2
internal_process_ops[0xbb]	1437	1			T1	8		T4	2		T8	1
internal_process_ops[0xeb]	1499	1			T1	9		T3	8		T10	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75151

1

T1

287

T3

16

T4

8

auto[1]

1436

1

T8

7

T10

7

T11

13

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73789

1

T1

279

T3

16

T4

8

auto[1]

2798

1

T1

8

T8

17

T10

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13151

1

T1

60

T7

4

T9

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6925

1

T1

14

T10

40

T24

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2640

1

T1

14

T4

2

T10

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2240

1

T1

14

T6

2

T10

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3343

1

T1

25

T4

4

T9

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2897

1

T1

16

T10

24

T24

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2747

1

T1

13

T4

2

T9

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2216

1

T1

17

T10

16

T32

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

108

1

T26

2

T28

1

T143

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

78

1

T17

2

T27

2

T132

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

72

1

T17

1

T28

1

T30

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T10

1

T24

4

T17

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

110

1

T17

2

T26

2

T27

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

92

1

T10

1

T17

3

T26

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

69

1

T10

2

T20

3

T30

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

77

1

T10

4

T17

1

T26

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T1

2

T17

1

T26

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

71

1

T30

4

T121

2

T144

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

65

1

T1

1

T10

3

T17

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

68

1

T17

1

T26

1

T28

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

117

1

T10

1

T17

3

T28

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

70

1

T30

2

T121

1

T145

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

80

1

T1

3

T10

1

T17

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

71

1

T10

1

T17

2

T26

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13928

1

T1

52

T8

105

T11

218

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

9464

1

T1

9

T8

121

T11

123

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2285

1

T1

8

T3

8

T8

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2079

1

T1

8

T8

1

T11

33

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2903

1

T1

7

T3

8

T8

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2597

1

T1

5

T8

9

T11

20

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2241

1

T1

6

T8

8

T11

38

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2006

1

T1

8

T8

3

T11

33

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

96

1

T1

1

T11

2

T23

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T22

1

T19

1

T60

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

98

1

T22

1

T19

1

T60

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

107

1

T22

2

T23

1

T40

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

87

1

T11

1

T22

1

T23

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

115

1

T11

1

T23

3

T40

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

93

1

T1

2

T22

1

T40

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

105

1

T8

3

T23

1

T41

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

94

1

T11

3

T60

1

T21

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T8

2

T11

3

T22

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

96

1

T1

1

T8

2

T11

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

109

1

T8

2

T23

2

T41

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

103

1

T1

1

T8

1

T41

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

75

1

T11

3

T23

2

T40

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

113

1

T11

3

T22

1

T23

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

104

1

T11

6

T19

1

T60

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	5183	1			T1	24		T10	27		T25	6
auto[0]	values[0]	valids[0x1]	18329	1			T1	62		T7	4		T9	10
auto[0]	values[1]	valids[0x1]	743	1			T1	1		T10	9		T32	4
auto[0]	values[2]	valids[0x0]	667	1			T1	2		T10	3		T17	12
auto[0]	values[2]	valids[0x1]	364	1			T1	2		T10	2		T17	3
auto[0]	values[3]	valids[0x0]	672	1			T1	5		T6	2		T10	4
auto[0]	values[3]	valids[0x1]	335	1			T1	2		T10	5		T17	8
auto[0]	values[4]	valids[0x0]	629	1			T1	5		T10	2		T33	2
auto[0]	values[4]	valids[0x1]	345	1			T10	6		T17	5		T26	2
auto[0]	values[5]	valids[0x0]	712	1			T1	3		T10	8		T17	5
auto[0]	values[5]	valids[0x1]	357	1			T1	4		T10	2		T17	1
auto[0]	values[6]	valids[0x0]	680	1			T1	7		T10	7		T17	3
auto[0]	values[6]	valids[0x1]	403	1			T1	8		T10	2		T17	1
auto[0]	values[7]	valids[0x0]	684	1			T1	3		T4	2		T10	3
auto[0]	values[7]	valids[0x1]	337	1			T1	1		T10	1		T24	2
auto[0]	values[8]	valids[0x0]	4438	1			T1	26		T4	2		T10	34
auto[0]	values[8]	valids[0x1]	2615	1			T1	24		T4	4		T9	2
auto[1]	values[0]	valids[0x0]	5821	1			T1	21		T8	26		T11	92
auto[1]	values[0]	valids[0x1]	21077	1			T1	48		T8	222		T11	304
auto[1]	values[1]	valids[0x1]	732	1			T1	7		T11	6		T22	6
auto[1]	values[2]	valids[0x0]	491	1			T1	1		T11	2		T22	3
auto[1]	values[2]	valids[0x1]	365	1			T8	1		T11	7		T22	3
auto[1]	values[3]	valids[0x0]	549	1			T8	4		T11	3		T22	6
auto[1]	values[3]	valids[0x1]	376	1			T1	1		T11	3		T22	1
auto[1]	values[4]	valids[0x0]	573	1			T1	1		T8	2		T11	13
auto[1]	values[4]	valids[0x1]	310	1			T1	1		T11	5		T22	2
auto[1]	values[5]	valids[0x0]	579	1			T1	3		T3	8		T8	4
auto[1]	values[5]	valids[0x1]	386	1			T11	10		T22	6		T23	2
auto[1]	values[6]	valids[0x0]	564	1			T1	4		T8	2		T11	5
auto[1]	values[6]	valids[0x1]	365	1			T1	1		T11	10		T22	2
auto[1]	values[7]	valids[0x0]	553	1			T1	2		T8	1		T11	14
auto[1]	values[7]	valids[0x1]	329	1			T1	2		T8	3		T11	5
auto[1]	values[8]	valids[0x0]	3545	1			T1	10		T3	8		T8	7
auto[1]	values[8]	valids[0x1]	2479	1			T1	6		T8	2		T11	34