Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20990

1

T1

88

T3

15

T4

4

auto[1]

26163

1

T1

55

T8

207

T10

258

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17727

1

T1

63

T3

15

T4

4

auto[1]

29426

1

T1

80

T8

201

T10

262

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7359	1			T1	7		T3	1		T4	3
auto[524288:1048575]	5690	1			T1	31		T8	40		T10	2
auto[1048576:1572863]	6547	1			T1	40		T3	5		T8	126
auto[1572864:2097151]	4976	1			T1	16		T10	20		T11	27
auto[2097152:2621439]	5906	1			T1	7		T3	2		T10	5
auto[2621440:3145727]	5930	1			T1	16		T3	3		T10	6
auto[3145728:3670015]	5233	1			T1	14		T3	3		T8	20
auto[3670016:4194303]	5512	1			T1	12		T3	1		T4	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46152

1

T1

142

T3

15

T4

4

auto[1]

1001

1

T1

1

T8

14

T10

6

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37059

1

T1

72

T3

15

T4

4

auto[1]

10094

1

T1

71

T8

17

T10

26

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1961	1			T1	2		T3	1		T4	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	823	1			T1	4		T10	7		T11	3
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1476	1			T1	7		T8	5		T10	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	575	1			T1	4		T8	2		T11	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1629	1			T1	3		T3	5		T8	11
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	603	1			T1	2		T8	2		T10	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1285	1			T1	4		T10	5		T11	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	491	1			T1	3		T10	2		T11	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1404	1			T3	2		T10	2		T11	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	551	1			T10	2		T22	1		T23	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1407	1			T1	3		T3	3		T10	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	559	1			T1	3		T10	1		T11	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1409	1			T3	3		T8	5		T11	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	536	1			T8	5		T10	1		T11	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1400	1			T1	3		T3	1		T4	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	591	1			T1	4		T8	2		T10	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	373	1			T1	1		T8	2		T10	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	169	1			T10	1		T11	6		T22	2
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	396	1			T1	12		T11	11		T17	10
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	162	1			T1	4		T11	7		T17	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	352	1			T1	3		T8	3		T11	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	153	1			T1	4		T11	1		T23	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	334	1			T1	3		T11	2		T22	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	173	1			T1	2		T11	2		T22	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	427	1			T1	7		T11	10		T22	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	177	1			T10	1		T11	4		T22	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	390	1			T1	1		T11	4		T22	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	186	1			T11	2		T23	1		T40	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	342	1			T1	5		T10	3		T22	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	152	1			T1	2		T22	4		T23	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	341	1			T1	1		T22	1		T23	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	163	1			T1	1		T23	1		T17	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	335	1			T8	2		T10	4		T11	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2906	1			T8	10		T10	122		T11	7
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	244	1			T1	1		T8	2		T11	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2152	1			T1	3		T8	31		T11	20
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	312	1			T1	2		T8	7		T10	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2733	1			T1	11		T8	91		T10	39
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	211	1			T1	1		T10	2		T11	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1983	1			T1	3		T10	11		T11	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	275	1			T11	1		T22	5		T23	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2160	1			T11	3		T22	33		T23	36
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	275	1			T1	1		T11	9		T22	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2018	1			T1	8		T11	49		T22	22
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	242	1			T8	3		T11	1		T22	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1834	1			T8	7		T11	2		T22	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	282	1			T8	2		T10	4		T22	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2397	1			T8	40		T10	54		T22	12
auto[1]	auto[1]	auto[0:524287]	auto[0]	82	1			T11	1		T22	1		T26	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	710	1			T11	2		T22	5		T26	7
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	82	1			T11	3		T17	5		T41	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	603	1			T11	67		T17	42		T41	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	67	1			T1	1		T8	1		T11	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	698	1			T1	14		T8	11		T11	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	63	1			T11	1		T18	1		T27	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	436	1			T11	5		T18	2		T27	13
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	98	1			T11	1		T17	1		T41	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	814	1			T11	7		T17	29		T41	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	94	1			T11	1		T19	1		T60	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1001	1			T11	1		T19	1		T60	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	82	1			T1	1		T10	1		T22	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	636	1			T1	6		T10	19		T22	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	57	1			T1	1		T23	1		T17	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	281	1			T1	2		T23	24		T17	6

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	16318	1			T1	41		T3	15		T4	4
auto[0]	auto[0]	auto[1]	382	1			T1	1		T8	4		T10	5
auto[0]	auto[1]	auto[0]	4175	1			T1	46		T8	4		T10	6
auto[0]	auto[1]	auto[1]	115	1			T8	1		T11	2		T23	2
auto[1]	auto[0]	auto[0]	19971	1			T1	30		T8	186		T10	237
auto[1]	auto[0]	auto[1]	388	1			T8	9		T10	1		T22	5
auto[1]	auto[1]	auto[0]	5688	1			T1	25		T8	12		T10	20
auto[1]	auto[1]	auto[1]	116	1			T11	2		T22	1		T17	1