Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22615

1

T1

114

T4

8

T7

4

auto[1]

14878

1

T1

65

T6

2

T10

99

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5188	1			T1	43		T6	2		T10	20
values[1]	4639	1			T1	40		T7	4		T10	20
values[2]	4194	1			T1	20		T10	57		T33	2
values[3]	4185	1			T1	26		T4	8		T86	10
values[4]	5503	1			T9	12		T10	181		T24	10
values[5]	4923	1			T1	30		T10	60		T32	6
values[6]	4737	1			T10	47		T17	67		T27	20
values[7]	4124	1			T1	20		T10	40		T17	113

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4326	1			T1	69		T10	20		T33	2
values[1]	4237	1			T1	20		T7	4		T10	20
values[2]	5066	1			T10	117		T17	142		T184	12
values[3]	4603	1			T1	40		T10	47		T17	209
values[4]	4713	1			T4	8		T9	12		T10	181
values[5]	4972	1			T32	6		T86	10		T17	41
values[6]	4830	1			T1	50		T10	20		T17	139
values[7]	4746	1			T6	2		T10	20		T17	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	454	1			T1	14		T34	16		T20	14
auto[0]	values[0]	values[1]	290	1			T10	14		T187	12		T181	12
auto[0]	values[0]	values[2]	306	1			T184	12		T37	15		T30	10
auto[0]	values[0]	values[3]	309	1			T1	13		T17	6		T26	14
auto[0]	values[0]	values[4]	322	1			T25	32		T198	34		T20	24
auto[0]	values[0]	values[5]	362	1			T26	16		T30	16		T191	36
auto[0]	values[0]	values[6]	602	1			T28	16		T199	8		T37	11
auto[0]	values[0]	values[7]	485	1			T37	9		T20	13		T132	11
auto[0]	values[1]	values[0]	383	1			T1	13		T121	12		T170	12
auto[0]	values[1]	values[1]	470	1			T7	4		T17	6		T30	82
auto[0]	values[1]	values[2]	540	1			T10	14		T17	13		T28	12
auto[0]	values[1]	values[3]	288	1			T1	8		T28	16		T167	22
auto[0]	values[1]	values[4]	295	1			T26	12		T27	11		T187	6
auto[0]	values[1]	values[5]	252	1			T30	10		T132	12		T163	18
auto[0]	values[1]	values[6]	297	1			T17	32		T200	8		T132	89
auto[0]	values[1]	values[7]	181	1			T27	12		T132	13		T160	13
auto[0]	values[2]	values[0]	166	1			T33	2		T30	12		T144	14
auto[0]	values[2]	values[1]	318	1			T1	11		T132	14		T160	8
auto[0]	values[2]	values[2]	332	1			T10	32		T17	22		T201	6
auto[0]	values[2]	values[3]	312	1			T26	80		T27	110		T202	12
auto[0]	values[2]	values[4]	472	1			T28	11		T20	12		T132	8
auto[0]	values[2]	values[5]	366	1			T20	26		T203	6		T121	9
auto[0]	values[2]	values[6]	300	1			T10	13		T204	6		T187	13
auto[0]	values[2]	values[7]	283	1			T17	11		T26	10		T205	23
auto[0]	values[3]	values[0]	422	1			T1	16		T37	12		T165	11
auto[0]	values[3]	values[1]	237	1			T17	9		T28	9		T37	17
auto[0]	values[3]	values[2]	462	1			T17	6		T26	11		T206	8
auto[0]	values[3]	values[3]	323	1			T28	13		T30	55		T132	29
auto[0]	values[3]	values[4]	141	1			T4	8		T121	13		T207	13
auto[0]	values[3]	values[5]	186	1			T86	10		T30	13		T158	13
auto[0]	values[3]	values[6]	258	1			T26	17		T208	8		T20	11
auto[0]	values[3]	values[7]	440	1			T28	10		T37	24		T20	24
auto[0]	values[4]	values[0]	261	1			T26	21		T20	8		T209	20
auto[0]	values[4]	values[1]	379	1			T26	23		T27	22		T37	5
auto[0]	values[4]	values[2]	291	1			T158	21		T160	105		T210	9
auto[0]	values[4]	values[3]	704	1			T17	21		T37	75		T20	14
auto[0]	values[4]	values[4]	572	1			T9	12		T10	170		T26	13
auto[0]	values[4]	values[5]	562	1			T139	4		T30	16		T211	2
auto[0]	values[4]	values[6]	472	1			T30	55		T158	11		T212	12
auto[0]	values[4]	values[7]	264	1			T140	6		T153	10		T158	11
auto[0]	values[5]	values[0]	347	1			T20	11		T121	12		T187	10
auto[0]	values[5]	values[1]	247	1			T144	11		T180	15		T151	15
auto[0]	values[5]	values[2]	463	1			T10	48		T213	10		T214	30
auto[0]	values[5]	values[3]	306	1			T26	11		T28	34		T163	13
auto[0]	values[5]	values[4]	383	1			T143	26		T180	21		T181	19
auto[0]	values[5]	values[5]	393	1			T17	37		T30	28		T155	18
auto[0]	values[5]	values[6]	414	1			T1	22		T17	42		T26	15
auto[0]	values[5]	values[7]	315	1			T26	15		T27	6		T196	10
auto[0]	values[6]	values[0]	353	1			T215	8		T166	16		T144	15
auto[0]	values[6]	values[1]	236	1			T27	12		T37	54		T168	8
auto[0]	values[6]	values[2]	381	1			T132	16		T160	13		T216	2
auto[0]	values[6]	values[3]	321	1			T10	12		T17	14		T20	10
auto[0]	values[6]	values[4]	374	1			T37	64		T30	13		T170	9
auto[0]	values[6]	values[5]	444	1			T20	10		T132	116		T165	13
auto[0]	values[6]	values[6]	290	1			T37	51		T20	9		T144	11
auto[0]	values[6]	values[7]	370	1			T158	18		T186	10		T121	12
auto[0]	values[7]	values[0]	232	1			T10	10		T26	12		T217	18
auto[0]	values[7]	values[1]	151	1			T106	12		T37	8		T132	11
auto[0]	values[7]	values[2]	294	1			T17	26		T218	10		T30	35
auto[0]	values[7]	values[3]	281	1			T17	4		T192	28		T159	22
auto[0]	values[7]	values[4]	442	1			T27	82		T158	9		T175	36
auto[0]	values[7]	values[5]	494	1			T27	14		T37	115		T177	6
auto[0]	values[7]	values[6]	388	1			T1	17		T17	44		T26	14
auto[0]	values[7]	values[7]	337	1			T10	13		T27	24		T37	15
auto[1]	values[0]	values[0]	229	1			T1	9		T20	13		T180	7
auto[1]	values[0]	values[1]	258	1			T10	6		T31	20		T187	12
auto[1]	values[0]	values[2]	295	1			T37	5		T30	42		T187	4
auto[1]	values[0]	values[3]	239	1			T1	7		T17	88		T26	6
auto[1]	values[0]	values[4]	192	1			T20	16		T132	8		T160	16
auto[1]	values[0]	values[5]	239	1			T26	4		T30	8		T180	73
auto[1]	values[0]	values[6]	225	1			T28	37		T29	16		T37	25
auto[1]	values[0]	values[7]	381	1			T6	2		T37	74		T20	7
auto[1]	values[1]	values[0]	279	1			T1	7		T121	11		T170	8
auto[1]	values[1]	values[1]	227	1			T17	20		T30	14		T187	7
auto[1]	values[1]	values[2]	294	1			T10	6		T17	29		T28	8
auto[1]	values[1]	values[3]	107	1			T1	12		T28	4		T158	10
auto[1]	values[1]	values[4]	280	1			T26	47		T27	68		T219	8
auto[1]	values[1]	values[5]	449	1			T30	10		T132	8		T163	71
auto[1]	values[1]	values[6]	174	1			T17	5		T132	24		T163	7
auto[1]	values[1]	values[7]	123	1			T27	23		T132	7		T160	7
auto[1]	values[2]	values[0]	124	1			T30	50		T144	8		T165	11
auto[1]	values[2]	values[1]	208	1			T1	9		T132	11		T160	12
auto[1]	values[2]	values[2]	217	1			T10	5		T17	18		T220	4
auto[1]	values[2]	values[3]	149	1			T26	27		T27	5		T221	11
auto[1]	values[2]	values[4]	190	1			T28	9		T20	8		T132	12
auto[1]	values[2]	values[5]	304	1			T20	2		T121	11		T163	6
auto[1]	values[2]	values[6]	224	1			T10	7		T187	10		T151	15
auto[1]	values[2]	values[7]	229	1			T17	9		T26	10		T158	4
auto[1]	values[3]	values[0]	331	1			T1	10		T37	54		T165	13
auto[1]	values[3]	values[1]	208	1			T17	16		T28	11		T37	19
auto[1]	values[3]	values[2]	205	1			T17	14		T26	9		T121	9
auto[1]	values[3]	values[3]	251	1			T28	56		T30	13		T132	5
auto[1]	values[3]	values[4]	108	1			T121	7		T207	7		T222	10
auto[1]	values[3]	values[5]	101	1			T30	7		T158	9		T144	11
auto[1]	values[3]	values[6]	212	1			T26	4		T20	12		T157	20
auto[1]	values[3]	values[7]	300	1			T28	10		T37	8		T20	2
auto[1]	values[4]	values[0]	142	1			T26	6		T20	12		T121	11
auto[1]	values[4]	values[1]	339	1			T26	21		T27	26		T37	76
auto[1]	values[4]	values[2]	283	1			T158	103		T160	7		T223	22
auto[1]	values[4]	values[3]	329	1			T17	7		T37	9		T20	9
auto[1]	values[4]	values[4]	226	1			T10	11		T24	10		T26	13
auto[1]	values[4]	values[5]	161	1			T30	4		T121	7		T159	6
auto[1]	values[4]	values[6]	225	1			T30	8		T158	32		T212	27
auto[1]	values[4]	values[7]	293	1			T158	9		T163	10		T165	11
auto[1]	values[5]	values[0]	327	1			T20	9		T121	18		T187	11
auto[1]	values[5]	values[1]	243	1			T144	9		T180	7		T151	5
auto[1]	values[5]	values[2]	313	1			T10	12		T144	7		T180	10
auto[1]	values[5]	values[3]	208	1			T26	29		T28	5		T163	7
auto[1]	values[5]	values[4]	240	1			T180	5		T181	10		T224	10
auto[1]	values[5]	values[5]	139	1			T32	6		T17	4		T30	11
auto[1]	values[5]	values[6]	380	1			T1	8		T17	7		T26	5
auto[1]	values[5]	values[7]	205	1			T26	5		T27	14		T180	5
auto[1]	values[6]	values[0]	178	1			T144	5		T159	10		T181	8
auto[1]	values[6]	values[1]	289	1			T27	8		T37	16		T163	5
auto[1]	values[6]	values[2]	229	1			T132	36		T160	38		T225	9
auto[1]	values[6]	values[3]	290	1			T10	35		T17	53		T20	10
auto[1]	values[6]	values[4]	266	1			T37	8		T30	21		T170	11
auto[1]	values[6]	values[5]	270	1			T20	10		T132	6		T165	7
auto[1]	values[6]	values[6]	181	1			T37	9		T20	11		T226	18
auto[1]	values[6]	values[7]	265	1			T158	2		T121	10		T151	8
auto[1]	values[7]	values[0]	98	1			T10	10		T26	11		T212	8
auto[1]	values[7]	values[1]	137	1			T37	12		T132	9		T187	11
auto[1]	values[7]	values[2]	161	1			T17	14		T30	16		T165	8
auto[1]	values[7]	values[3]	186	1			T17	16		T159	24		T151	7
auto[1]	values[7]	values[4]	210	1			T27	16		T158	15		T160	9
auto[1]	values[7]	values[5]	250	1			T27	18		T37	8		T160	7
auto[1]	values[7]	values[6]	188	1			T1	3		T17	9		T26	6
auto[1]	values[7]	values[7]	275	1			T10	7		T27	16		T37	55