Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	524	1			T1	2		T10	3		T17	4
auto[ReadAddrCrossIntoMailbox]	401	1			T1	6		T4	4		T10	6
auto[ReadAddrCrossOutOfMailbox]	460	1			T1	3		T10	7		T17	1
auto[ReadAddrCrossAllMailbox]	273	1			T4	2		T17	2		T26	4
auto[ReadAddrOutsideMailbox]	4429	1			T1	27		T4	2		T9	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3060

1

T1

22

T4

4

T9

1

auto[1]

3027

1

T1

16

T4

4

T9

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	995	1			T1	7		T10	5		T24	2
read_ops[0x0b]	995	1			T1	9		T4	4		T9	2
read_ops[0x3b]	1096	1			T1	5		T10	9		T34	4
read_ops[0x6b]	995	1			T1	4		T4	2		T10	4
read_ops[0xbb]	968	1			T1	6		T4	2		T10	7
read_ops[0xeb]	1038	1			T1	7		T10	10		T34	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	48	1			T27	2		T37	1		T20	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T10	1		T26	1		T27	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T20	2		T145	1		T163	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	39	1			T10	1		T26	1		T121	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T10	1		T27	1		T37	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	45	1			T1	1		T26	2		T27	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T17	1		T30	1		T145	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T26	2		T165	1		T202	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	344	1			T1	4		T24	1		T17	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	371	1			T1	2		T10	2		T24	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	52	1			T1	1		T17	1		T27	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	53	1			T199	1		T121	1		T160	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T1	1		T4	1		T10	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T4	1		T145	1		T170	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T1	1		T10	1		T28	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T10	1		T37	3		T20	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T4	1		T30	1		T227	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T4	1		T26	1		T227	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	382	1			T1	5		T9	1		T10	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	340	1			T1	1		T9	1		T10	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T185	2		T20	2		T121	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T37	1		T185	2		T121	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	37	1			T1	1		T10	2		T17	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T26	1		T28	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	48	1			T10	1		T27	3		T199	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T26	1		T199	2		T20	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T186	2		T121	1		T160	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T37	1		T186	2		T144	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	416	1			T1	4		T10	3		T34	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	388	1			T10	3		T34	2		T25	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T17	1		T26	1		T27	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T1	1		T27	1		T37	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T1	1		T17	2		T26	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	39	1			T1	1		T27	1		T37	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T17	1		T27	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	42	1			T27	3		T28	1		T37	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	30	1			T17	1		T20	1		T159	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T26	1		T37	1		T30	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	377	1			T1	1		T4	1		T10	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T4	1		T10	2		T25	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T17	1		T26	1		T37	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T10	1		T27	1		T20	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T4	1		T26	1		T27	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T4	1		T28	1		T30	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	43	1			T26	1		T27	1		T20	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T10	1		T27	1		T20	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T199	1		T37	2		T180	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T27	2		T199	1		T30	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	353	1			T1	1		T10	2		T86	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	360	1			T1	5		T10	3		T86	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	52	1			T17	1		T37	1		T159	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T10	1		T20	1		T160	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T1	1		T10	2		T28	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T1	1		T26	1		T30	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T10	2		T26	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T1	1		T26	2		T27	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T196	1		T121	1		T132	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T196	1		T159	1		T164	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	353	1			T1	1		T10	2		T34	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	410	1			T1	3		T10	3		T34	3