Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	9410364	1			T1	6167		T2	6865		T3	4095
all_pins[1]	9410364	1			T1	6167		T2	6865		T3	4095
all_pins[2]	9410364	1			T1	6167		T2	6865		T3	4095
all_pins[3]	9410364	1			T1	6167		T2	6865		T3	4095
all_pins[4]	9410364	1			T1	6167		T2	6865		T3	4095
all_pins[5]	9410364	1			T1	6167		T2	6865		T3	4095
all_pins[6]	9410364	1			T1	6167		T2	6865		T3	4095
all_pins[7]	9410364	1			T1	6167		T2	6865		T3	4095

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	74899044	1			T1	49336		T2	54920		T3	32760
values[0x1]	383868	1			T26	51		T19	11		T59	24
transitions[0x0=>0x1]	381031	1			T26	36		T19	6		T59	18
transitions[0x1=>0x0]	381042	1			T26	36		T19	6		T59	18

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	9408224	1			T1	6167		T2	6865		T3	4095
all_pins[0]	values[0x1]	2140	1			T26	7		T59	2		T60	2
all_pins[0]	transitions[0x0=>0x1]	1792	1			T26	5		T59	2		T60	1
all_pins[0]	transitions[0x1=>0x0]	136	1			T26	4		T19	1		T59	1
all_pins[1]	values[0x0]	9409880	1			T1	6167		T2	6865		T3	4095
all_pins[1]	values[0x1]	484	1			T26	6		T19	1		T59	1
all_pins[1]	transitions[0x0=>0x1]	427	1			T26	5		T59	1		T60	1
all_pins[1]	transitions[0x1=>0x0]	209	1			T26	5		T59	3		T60	2
all_pins[2]	values[0x0]	9410098	1			T1	6167		T2	6865		T3	4095
all_pins[2]	values[0x1]	266	1			T26	6		T19	1		T59	3
all_pins[2]	transitions[0x0=>0x1]	217	1			T26	6		T59	2		T60	3
all_pins[2]	transitions[0x1=>0x0]	159	1			T26	6		T19	2		T59	4
all_pins[3]	values[0x0]	9410156	1			T1	6167		T2	6865		T3	4095
all_pins[3]	values[0x1]	208	1			T26	6		T19	3		T59	5
all_pins[3]	transitions[0x0=>0x1]	149	1			T26	6		T59	2		T60	2
all_pins[3]	transitions[0x1=>0x0]	138	1			T26	2		T59	1		T60	3
all_pins[4]	values[0x0]	9410167	1			T1	6167		T2	6865		T3	4095
all_pins[4]	values[0x1]	197	1			T26	2		T19	3		T59	4
all_pins[4]	transitions[0x0=>0x1]	159	1			T26	1		T19	3		T59	4
all_pins[4]	transitions[0x1=>0x0]	6071	1			T26	3		T59	1		T60	1
all_pins[5]	values[0x0]	9404255	1			T1	6167		T2	6865		T3	4095
all_pins[5]	values[0x1]	6109	1			T26	4		T59	1		T60	2
all_pins[5]	transitions[0x0=>0x1]	3946	1			T26	2		T59	1		T60	2
all_pins[5]	transitions[0x1=>0x0]	372093	1			T26	10		T59	2		T60	2
all_pins[6]	values[0x0]	9036108	1			T1	6167		T2	6865		T3	4095
all_pins[6]	values[0x1]	374256	1			T26	12		T59	2		T60	2
all_pins[6]	transitions[0x0=>0x1]	374197	1			T26	6		T59	1		T60	2
all_pins[6]	transitions[0x1=>0x0]	149	1			T26	2		T19	3		T59	5
all_pins[7]	values[0x0]	9410156	1			T1	6167		T2	6865		T3	4095
all_pins[7]	values[0x1]	208	1			T26	8		T19	3		T59	6
all_pins[7]	transitions[0x0=>0x1]	144	1			T26	5		T19	3		T59	5
all_pins[7]	transitions[0x1=>0x0]	2087	1			T26	4		T59	1		T60	1