Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4615	1			T1	20		T7	4		T10	47
values[1]	4698	1			T1	20		T6	2		T9	12
values[2]	4871	1			T1	20		T10	100		T32	6
values[3]	4911	1			T1	30		T10	20		T33	2
values[4]	5193	1			T10	37		T17	118		T26	24
values[5]	4369	1			T1	20		T4	8		T10	201
values[6]	4181	1			T1	43		T17	46		T184	12
values[7]	4655	1			T1	26		T10	20		T25	32

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4390	1			T1	50		T10	40		T86	10
values[1]	4840	1			T1	20		T6	2		T10	20
values[2]	4795	1			T1	46		T32	6		T24	10
values[3]	4676	1			T1	23		T17	187		T198	34
values[4]	5145	1			T1	20		T4	8		T10	80
values[5]	4829	1			T7	4		T10	37		T34	16
values[6]	4436	1			T10	248		T25	32		T17	69
values[7]	4382	1			T1	20		T9	12		T33	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36868

1

T1

179

T4

8

T6

2

auto[1]

625

1

T10

7

T24

4

T17

10

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	548	1			T1	20		T26	20		T20	20
auto[0]	values[0]	values[1]	607	1			T17	19		T37	119		T228	4
auto[0]	values[0]	values[2]	441	1			T106	12		T206	8		T20	20
auto[0]	values[0]	values[3]	568	1			T153	10		T37	70		T229	12
auto[0]	values[0]	values[4]	811	1			T26	64		T27	77		T28	53
auto[0]	values[0]	values[5]	579	1			T7	4		T34	16		T37	84
auto[0]	values[0]	values[6]	474	1			T10	47		T26	20		T37	32
auto[0]	values[0]	values[7]	525	1			T132	86		T187	20		T159	21
auto[0]	values[1]	values[0]	353	1			T121	26		T160	23		T212	22
auto[0]	values[1]	values[1]	753	1			T6	2		T37	36		T20	20
auto[0]	values[1]	values[2]	484	1			T1	20		T17	20		T208	8
auto[0]	values[1]	values[3]	401	1			T211	2		T163	23		T187	47
auto[0]	values[1]	values[4]	697	1			T36	28		T203	6		T152	14
auto[0]	values[1]	values[5]	635	1			T26	26		T158	20		T196	10
auto[0]	values[1]	values[6]	750	1			T26	21		T27	79		T121	20
auto[0]	values[1]	values[7]	554	1			T9	12		T26	40		T28	20
auto[0]	values[2]	values[0]	394	1			T17	42		T121	30		T230	8
auto[0]	values[2]	values[1]	783	1			T10	20		T17	20		T28	68
auto[0]	values[2]	values[2]	709	1			T32	6		T27	20		T158	20
auto[0]	values[2]	values[3]	466	1			T20	26		T168	8		T180	20
auto[0]	values[2]	values[4]	702	1			T1	20		T10	79		T26	20
auto[0]	values[2]	values[5]	688	1			T158	31		T174	20		T144	40
auto[0]	values[2]	values[6]	414	1			T20	27		T204	6		T180	20
auto[0]	values[2]	values[7]	631	1			T26	20		T139	4		T185	16
auto[0]	values[3]	values[0]	506	1			T1	30		T20	27		T180	39
auto[0]	values[3]	values[1]	553	1			T30	20		T132	21		T181	21
auto[0]	values[3]	values[2]	862	1			T24	6		T17	35		T27	20
auto[0]	values[3]	values[3]	849	1			T17	91		T30	38		T227	16
auto[0]	values[3]	values[4]	789	1			T26	77		T20	22		T30	105
auto[0]	values[3]	values[5]	465	1			T26	20		T200	8		T31	18
auto[0]	values[3]	values[6]	388	1			T10	20		T17	48		T165	22
auto[0]	values[3]	values[7]	410	1			T33	2		T17	27		T205	23
auto[0]	values[4]	values[0]	698	1			T20	36		T158	22		T180	44
auto[0]	values[4]	values[1]	647	1			T27	54		T28	20		T29	14
auto[0]	values[4]	values[2]	709	1			T17	20		T27	71		T20	20
auto[0]	values[4]	values[3]	663	1			T30	61		T186	10		T187	20
auto[0]	values[4]	values[4]	624	1			T17	24		T27	49		T37	132
auto[0]	values[4]	values[5]	555	1			T10	36		T17	52		T20	33
auto[0]	values[4]	values[6]	408	1			T17	20		T26	23		T180	20
auto[0]	values[4]	values[7]	794	1			T27	47		T30	23		T132	20
auto[0]	values[5]	values[0]	495	1			T10	20		T231	4		T165	19
auto[0]	values[5]	values[1]	381	1			T26	20		T27	20		T20	20
auto[0]	values[5]	values[2]	450	1			T26	20		T28	73		T160	29
auto[0]	values[5]	values[3]	557	1			T17	67		T217	18		T121	20
auto[0]	values[5]	values[4]	628	1			T4	8		T28	20		T232	43
auto[0]	values[5]	values[5]	712	1			T17	41		T213	10		T30	20
auto[0]	values[5]	values[6]	654	1			T10	176		T160	112		T163	20
auto[0]	values[5]	values[7]	432	1			T1	20		T28	38		T20	20
auto[0]	values[6]	values[0]	679	1			T37	143		T20	20		T220	4
auto[0]	values[6]	values[1]	385	1			T1	20		T17	20		T26	25
auto[0]	values[6]	values[2]	538	1			T26	23		T215	8		T159	38
auto[0]	values[6]	values[3]	615	1			T1	23		T17	26		T198	34
auto[0]	values[6]	values[4]	462	1			T162	32		T233	2		T165	23
auto[0]	values[6]	values[5]	561	1			T30	19		T158	19		T132	20
auto[0]	values[6]	values[6]	443	1			T184	12		T218	10		T37	81
auto[0]	values[6]	values[7]	422	1			T199	8		T167	22		T187	21
auto[0]	values[7]	values[0]	659	1			T10	20		T86	10		T37	20
auto[0]	values[7]	values[1]	652	1			T26	21		T27	110		T28	20
auto[0]	values[7]	values[2]	501	1			T1	26		T140	6		T20	23
auto[0]	values[7]	values[3]	497	1			T20	20		T30	33		T212	49
auto[0]	values[7]	values[4]	357	1			T17	20		T26	20		T30	26
auto[0]	values[7]	values[5]	543	1			T37	48		T30	36		T234	4
auto[0]	values[7]	values[6]	835	1			T25	32		T28	19		T37	66
auto[0]	values[7]	values[7]	523	1			T182	22		T163	77		T180	32
auto[1]	values[0]	values[0]	5	1			T30	1		T165	1		T181	1
auto[1]	values[0]	values[1]	11	1			T17	1		T161	1		T235	1
auto[1]	values[0]	values[2]	9	1			T187	1		T164	2		T236	1
auto[1]	values[0]	values[3]	5	1			T163	2		T181	1		T47	1
auto[1]	values[0]	values[4]	13	1			T26	2		T27	1		T159	3
auto[1]	values[0]	values[5]	3	1			T170	1		T237	1		T238	1
auto[1]	values[0]	values[6]	5	1			T212	1		T47	1		T238	2
auto[1]	values[0]	values[7]	11	1			T132	3		T47	2		T239	2
auto[1]	values[1]	values[0]	7	1			T121	1		T160	1		T225	1
auto[1]	values[1]	values[1]	8	1			T30	1		T181	1		T212	2
auto[1]	values[1]	values[2]	7	1			T240	1		T222	1		T241	1
auto[1]	values[1]	values[3]	9	1			T163	1		T187	2		T48	1
auto[1]	values[1]	values[4]	5	1			T149	1		T242	1		T243	2
auto[1]	values[1]	values[5]	15	1			T121	3		T149	2		T236	3
auto[1]	values[1]	values[6]	6	1			T244	2		T49	1		T245	1
auto[1]	values[1]	values[7]	14	1			T180	5		T222	1		T49	3
auto[1]	values[2]	values[0]	7	1			T246	1		T47	4		T135	1
auto[1]	values[2]	values[1]	12	1			T28	1		T163	1		T181	1
auto[1]	values[2]	values[2]	18	1			T144	2		T165	1		T221	1
auto[1]	values[2]	values[3]	6	1			T151	4		T244	1		T247	1
auto[1]	values[2]	values[4]	12	1			T10	1		T248	2		T45	2
auto[1]	values[2]	values[5]	8	1			T159	2		T212	3		T150	2
auto[1]	values[2]	values[6]	6	1			T20	1		T212	1		T47	1
auto[1]	values[2]	values[7]	15	1			T30	1		T180	4		T49	2
auto[1]	values[3]	values[0]	2	1			T180	1		T249	1		-	-
auto[1]	values[3]	values[1]	9	1			T181	1		T164	1		T212	4
auto[1]	values[3]	values[2]	22	1			T24	4		T17	2		T189	1
auto[1]	values[3]	values[3]	13	1			T17	3		T30	1		T144	1
auto[1]	values[3]	values[4]	10	1			T26	2		T20	1		T30	2
auto[1]	values[3]	values[5]	7	1			T31	2		T170	1		T181	1
auto[1]	values[3]	values[6]	21	1			T17	1		T165	3		T164	6
auto[1]	values[3]	values[7]	5	1			T17	1		T163	1		T161	1
auto[1]	values[4]	values[0]	11	1			T180	3		T246	3		T250	2
auto[1]	values[4]	values[1]	13	1			T27	1		T29	2		T163	2
auto[1]	values[4]	values[2]	13	1			T27	1		T165	4		T251	2
auto[1]	values[4]	values[3]	6	1			T30	2		T187	1		T165	1
auto[1]	values[4]	values[4]	9	1			T17	1		T187	1		T221	3
auto[1]	values[4]	values[5]	16	1			T10	1		T17	1		T20	1
auto[1]	values[4]	values[6]	9	1			T26	1		T252	1		T253	4
auto[1]	values[4]	values[7]	18	1			T27	1		T30	1		T180	2
auto[1]	values[5]	values[0]	3	1			T165	1		T244	1		T137	1
auto[1]	values[5]	values[1]	7	1			T160	1		T170	2		T159	1
auto[1]	values[5]	values[2]	9	1			T190	1		T235	1		T173	1
auto[1]	values[5]	values[3]	6	1			T121	2		T159	2		T254	2
auto[1]	values[5]	values[4]	11	1			T132	1		T159	1		T164	1
auto[1]	values[5]	values[5]	11	1			T255	2		T246	2		T247	3
auto[1]	values[5]	values[6]	9	1			T10	5		T252	1		T256	3
auto[1]	values[5]	values[7]	4	1			T28	1		T187	1		T257	1
auto[1]	values[6]	values[0]	11	1			T180	1		T149	1		T207	1
auto[1]	values[6]	values[1]	3	1			T26	2		T145	1		-	-
auto[1]	values[6]	values[2]	15	1			T159	6		T164	2		T222	3
auto[1]	values[6]	values[3]	6	1			T20	1		T161	1		T47	1
auto[1]	values[6]	values[4]	11	1			T165	1		T257	1		T258	2
auto[1]	values[6]	values[5]	17	1			T30	1		T158	1		T180	1
auto[1]	values[6]	values[6]	3	1			T49	1		T245	1		T243	1
auto[1]	values[6]	values[7]	10	1			T222	2		T150	2		T135	4
auto[1]	values[7]	values[0]	12	1			T30	1		T121	2		T163	1
auto[1]	values[7]	values[1]	16	1			T27	5		T158	1		T259	1
auto[1]	values[7]	values[2]	8	1			T158	1		T180	1		T181	1
auto[1]	values[7]	values[3]	9	1			T30	1		T190	1		T45	3
auto[1]	values[7]	values[4]	4	1			T173	1		T260	1		T261	1
auto[1]	values[7]	values[5]	14	1			T30	2		T132	2		T181	1
auto[1]	values[7]	values[6]	11	1			T28	1		T163	1		T262	1
auto[1]	values[7]	values[7]	14	1			T180	2		T151	1		T45	1