Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2724

1

T1

8

T2

10

T12

4

auto[1]

2793

1

T1

3

T2

11

T12

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2920

1

T1

11

T2

11

T11

23

auto[1]

2597

1

T2

10

T12

6

T14

31

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4408

1

T1

4

T2

13

T12

6

auto[1]

1109

1

T1

7

T2

8

T11

8

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1121	1			T1	5		T2	5		T12	3
valid[1]	1055	1			T2	3		T11	3		T14	6
valid[2]	1124	1			T1	3		T2	4		T11	8
valid[3]	1117	1			T1	3		T2	7		T12	1
valid[4]	1100	1			T2	2		T12	2		T11	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	180	1			T11	1		T18	3		T39	1
auto[0]	auto[0]	valid[0]	auto[1]	253	1			T12	2		T14	3		T38	6
auto[0]	auto[0]	valid[1]	auto[0]	164	1			T11	1		T18	2		T39	1
auto[0]	auto[0]	valid[1]	auto[1]	249	1			T2	2		T14	3		T38	3
auto[0]	auto[0]	valid[2]	auto[0]	187	1			T1	1		T2	2		T11	4
auto[0]	auto[0]	valid[2]	auto[1]	261	1			T2	1		T14	2		T38	5
auto[0]	auto[0]	valid[3]	auto[0]	185	1			T1	1		T11	2		T18	1
auto[0]	auto[0]	valid[3]	auto[1]	257	1			T2	1		T12	1		T14	4
auto[0]	auto[0]	valid[4]	auto[0]	182	1			T18	1		T39	2		T41	2
auto[0]	auto[0]	valid[4]	auto[1]	256	1			T2	2		T12	1		T14	3
auto[0]	auto[1]	valid[0]	auto[0]	164	1			T1	2		T11	2		T18	1
auto[0]	auto[1]	valid[0]	auto[1]	300	1			T2	3		T12	1		T14	3
auto[0]	auto[1]	valid[1]	auto[0]	196	1			T11	1		T18	3		T39	1
auto[0]	auto[1]	valid[1]	auto[1]	251	1			T14	3		T38	5		T26	1
auto[0]	auto[1]	valid[2]	auto[0]	185	1			T11	2		T18	2		T39	2
auto[0]	auto[1]	valid[2]	auto[1]	263	1			T14	5		T38	3		T19	2
auto[0]	auto[1]	valid[3]	auto[0]	191	1			T2	1		T11	1		T18	3
auto[0]	auto[1]	valid[3]	auto[1]	256	1			T2	1		T14	2		T38	1
auto[0]	auto[1]	valid[4]	auto[0]	177	1			T11	1		T18	3		T39	1
auto[0]	auto[1]	valid[4]	auto[1]	251	1			T12	1		T14	3		T38	5
auto[1]	auto[0]	valid[0]	auto[0]	126	1			T1	2		T18	1		T26	1
auto[1]	auto[0]	valid[1]	auto[0]	90	1			T18	2		T26	1		T41	1
auto[1]	auto[0]	valid[2]	auto[0]	101	1			T1	2		T39	2		T26	3
auto[1]	auto[0]	valid[3]	auto[0]	117	1			T1	2		T2	2		T39	2
auto[1]	auto[0]	valid[4]	auto[0]	116	1			T11	2		T18	2		T85	1
auto[1]	auto[1]	valid[0]	auto[0]	98	1			T1	1		T2	2		T11	1
auto[1]	auto[1]	valid[1]	auto[0]	105	1			T2	1		T11	1		T17	1
auto[1]	auto[1]	valid[2]	auto[0]	127	1			T2	1		T11	2		T39	1
auto[1]	auto[1]	valid[3]	auto[0]	111	1			T2	2		T11	2		T39	1
auto[1]	auto[1]	valid[4]	auto[0]	118	1			T18	2		T39	1		T26	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal