Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74065

1

T1

349

T2

411

T13

10

auto[1]

26726

1

T2

126

T12

6

T14

399

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73949

1

T1

232

T2

350

T12

6

auto[1]

26842

1

T1

117

T2

187

T13

3

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	51888	1			T1	178		T2	275		T12	6
others[1]	8472	1			T1	24		T2	40		T13	1
others[2]	8654	1			T1	30		T2	54		T13	1
others[3]	9581	1			T1	26		T2	50		T13	2
interest[1]	5500	1			T1	25		T2	34		T13	1
interest[4]	33657	1			T1	121		T2	171		T12	6
interest[64]	16696	1			T1	66		T2	84		T11	88

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	24236	1			T1	117		T2	120		T13	3
auto[0]	auto[0]	others[1]	4016	1			T1	19		T2	18		T13	1
auto[0]	auto[0]	others[2]	4073	1			T1	21		T2	19		T13	1
auto[0]	auto[0]	others[3]	4448	1			T1	18		T2	21		T13	1
auto[0]	auto[0]	interest[1]	2592	1			T1	18		T2	15		T13	1
auto[0]	auto[0]	interest[4]	15627	1			T1	78		T2	76		T13	1
auto[0]	auto[0]	interest[64]	7858	1			T1	39		T2	31		T11	62
auto[0]	auto[1]	others[0]	13976	1			T2	63		T12	6		T14	212
auto[0]	auto[1]	others[1]	2241	1			T2	15		T14	34		T17	1
auto[0]	auto[1]	others[2]	2235	1			T2	10		T14	34		T38	24
auto[0]	auto[1]	others[3]	2521	1			T2	9		T14	36		T38	34
auto[0]	auto[1]	interest[1]	1432	1			T2	7		T14	21		T38	17
auto[0]	auto[1]	interest[4]	9236	1			T2	41		T12	6		T14	147
auto[0]	auto[1]	interest[64]	4321	1			T2	22		T14	62		T17	2
auto[1]	auto[0]	others[0]	13676	1			T1	61		T2	92		T13	2
auto[1]	auto[0]	others[1]	2215	1			T1	5		T2	7		T11	7
auto[1]	auto[0]	others[2]	2346	1			T1	9		T2	25		T11	24
auto[1]	auto[0]	others[3]	2612	1			T1	8		T2	20		T13	1
auto[1]	auto[0]	interest[1]	1476	1			T1	7		T2	12		T11	11
auto[1]	auto[0]	interest[4]	8794	1			T1	43		T2	54		T13	1
auto[1]	auto[0]	interest[64]	4517	1			T1	27		T2	31		T11	26

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal