Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	806	1			T26	21		T19	4		T59	14
all_values[1]	806	1			T26	21		T19	4		T59	14
all_values[2]	806	1			T26	21		T19	4		T59	14
all_values[3]	806	1			T26	21		T19	4		T59	14
all_values[4]	806	1			T26	21		T19	4		T59	14
all_values[5]	806	1			T26	21		T19	4		T59	14
all_values[6]	806	1			T26	21		T19	4		T59	14
all_values[7]	806	1			T26	21		T19	4		T59	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3330

1

T26

80

T19

24

T59

67

auto[1]

3118

1

T26

88

T19

8

T59

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2565

1

T26

63

T19

9

T59

51

auto[1]

3883

1

T26

105

T19

23

T59

61

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3698

1

T26

99

T19

16

T59

68

auto[1]

2750

1

T26

69

T19

16

T59

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	148	1			T26	4		T19	2		T59	2
all_values[0]	auto[0]	auto[0]	auto[1]	93	1			T26	4		T59	3		T60	2
all_values[0]	auto[0]	auto[1]	auto[0]	131	1			T141	5		T132	5		T142	2
all_values[0]	auto[0]	auto[1]	auto[1]	74	1			T26	6		T59	1		T60	1
all_values[0]	auto[1]	auto[0]	auto[1]	197	1			T26	5		T19	2		T59	5
all_values[0]	auto[1]	auto[1]	auto[1]	163	1			T26	2		T59	3		T60	3
all_values[1]	auto[0]	auto[0]	auto[0]	158	1			T26	4		T59	1		T60	1
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T26	4		T19	1		T59	1
all_values[1]	auto[0]	auto[1]	auto[0]	160	1			T26	3		T59	6		T60	1
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T26	3		T59	1		T141	1
all_values[1]	auto[1]	auto[0]	auto[1]	163	1			T26	4		T19	2		T59	2
all_values[1]	auto[1]	auto[1]	auto[1]	162	1			T26	3		T19	1		T59	3
all_values[2]	auto[0]	auto[0]	auto[0]	158	1			T26	2		T19	1		T59	4
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T26	1		T19	1		T59	1
all_values[2]	auto[0]	auto[1]	auto[0]	132	1			T26	4		T59	3		T60	2
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T26	3		T59	1		T60	1
all_values[2]	auto[1]	auto[0]	auto[1]	197	1			T26	4		T19	2		T59	3
all_values[2]	auto[1]	auto[1]	auto[1]	170	1			T26	7		T59	2		T60	4
all_values[3]	auto[0]	auto[0]	auto[0]	146	1			T26	5		T59	2		T60	5
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T26	1		T59	1		T141	3
all_values[3]	auto[0]	auto[1]	auto[0]	130	1			T26	4		T59	2		T141	4
all_values[3]	auto[0]	auto[1]	auto[1]	88	1			T26	4		T19	2		T59	2
all_values[3]	auto[1]	auto[0]	auto[1]	185	1			T26	4		T19	2		T59	4
all_values[3]	auto[1]	auto[1]	auto[1]	169	1			T26	3		T59	3		T60	2
all_values[4]	auto[0]	auto[0]	auto[0]	151	1			T26	6		T59	3		T141	4
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T26	1		T59	1		T60	3
all_values[4]	auto[0]	auto[1]	auto[0]	158	1			T26	4		T59	3		T60	1
all_values[4]	auto[0]	auto[1]	auto[1]	88	1			T26	1		T19	1		T59	2
all_values[4]	auto[1]	auto[0]	auto[1]	154	1			T26	4		T19	2		T59	4
all_values[4]	auto[1]	auto[1]	auto[1]	171	1			T26	5		T19	1		T59	1
all_values[5]	auto[0]	auto[0]	auto[0]	272	1			T26	9		T19	3		T59	9
all_values[5]	auto[0]	auto[1]	auto[0]	206	1			T26	5		T59	2		T60	2
all_values[5]	auto[1]	auto[0]	auto[1]	169	1			T26	3		T19	1		T59	3
all_values[5]	auto[1]	auto[1]	auto[1]	159	1			T26	4		T60	3		T141	3
all_values[6]	auto[0]	auto[0]	auto[0]	154	1			T26	2		T19	2		T59	7
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T26	1		T60	1		T141	3
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T26	2		T19	1		T59	3
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T26	4		T60	1		T141	1
all_values[6]	auto[1]	auto[0]	auto[1]	171	1			T26	6		T19	1		T59	2
all_values[6]	auto[1]	auto[1]	auto[1]	177	1			T26	6		T59	2		T60	2
all_values[7]	auto[0]	auto[0]	auto[0]	166	1			T26	4		T59	3		T60	1
all_values[7]	auto[0]	auto[0]	auto[1]	67	1			T26	1		T59	1		T60	1
all_values[7]	auto[0]	auto[1]	auto[0]	154	1			T26	5		T59	1		T60	3
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T26	2		T19	2		T59	2
all_values[7]	auto[1]	auto[0]	auto[1]	168	1			T26	1		T19	2		T59	5
all_values[7]	auto[1]	auto[1]	auto[1]	175	1			T26	8		T59	2		T141	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal