Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6981052	1			T1	1		T2	1		T3	1
all_values[1]	6981052	1			T1	1		T2	1		T3	1
all_values[2]	6981052	1			T1	1		T2	1		T3	1
all_values[3]	6981052	1			T1	1		T2	1		T3	1
all_values[4]	6981052	1			T1	1		T2	1		T3	1
all_values[5]	6981052	1			T1	1		T2	1		T3	1
all_values[6]	6981052	1			T1	1		T2	1		T3	1
all_values[7]	6981052	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55486323

1

T1

8

T2

8

T3

8

auto[1]

362093

1

T19

223993

T24

75

T44

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55776313

1

T1

8

T2

8

T3

8

auto[1]

72103

1

T5

435

T7

50

T9

252

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6894314	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	41416	1			T5	278		T7	25		T9	118
all_values[0]	auto[1]	auto[0]	44939	1			T19	44615		T24	4		T35	5
all_values[0]	auto[1]	auto[1]	383	1			T19	181		T24	4		T35	1
all_values[1]	auto[0]	auto[0]	6945278	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	20164	1			T5	140		T7	25		T9	106
all_values[1]	auto[1]	auto[0]	15390	1			T19	2		T24	4		T44	1
all_values[1]	auto[1]	auto[1]	220	1			T19	3		T24	6		T35	1
all_values[2]	auto[0]	auto[0]	6915779	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	7268	1			T5	17		T9	28		T15	8
all_values[2]	auto[1]	auto[0]	57779	1			T19	44785		T24	3		T35	11322
all_values[2]	auto[1]	auto[1]	226	1			T19	12		T24	6		T44	1
all_values[3]	auto[0]	auto[0]	6965212	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	199	1			T19	3		T24	5		T44	3
all_values[3]	auto[1]	auto[0]	15397	1			T19	6		T24	7		T44	1
all_values[3]	auto[1]	auto[1]	244	1			T19	10		T24	7		T35	2
all_values[4]	auto[0]	auto[0]	6891353	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	263	1			T19	6		T24	5		T44	1
all_values[4]	auto[1]	auto[0]	89234	1			T19	44787		T24	6		T44	5
all_values[4]	auto[1]	auto[1]	202	1			T19	4		T24	2		T44	1
all_values[5]	auto[0]	auto[0]	6922621	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	408	1			T19	5		T23	2		T24	6
all_values[5]	auto[1]	auto[0]	57816	1			T19	44790		T24	2		T35	11324
all_values[5]	auto[1]	auto[1]	207	1			T19	2		T24	5		T35	3
all_values[6]	auto[0]	auto[0]	6976545	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	210	1			T19	3		T24	5		T44	2
all_values[6]	auto[1]	auto[0]	4057	1			T19	1		T24	4		T35	2
all_values[6]	auto[1]	auto[1]	240	1			T19	5		T24	4		T44	1
all_values[7]	auto[0]	auto[0]	6905075	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	218	1			T19	7		T24	8		T35	4
all_values[7]	auto[1]	auto[0]	75524	1			T19	44786		T24	6		T44	5
all_values[7]	auto[1]	auto[1]	235	1			T19	4		T24	5		T44	1