Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	39727	1			T5	473		T7	21		T9	173
auto[SpiFlashAddrCfg]	8674	1			T5	65		T7	8		T9	17
auto[SpiFlashAddr3b]	10450	1			T3	4		T5	90		T7	9
auto[SpiFlashAddr4b]	8976	1			T5	67		T7	6		T9	24

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38179

1

T3

4

T5

337

T7

34

auto[1]

29648

1

T5

358

T7

10

T9

73

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34910

1

T3

4

T5

358

T7

33

auto[1]

32917

1

T5

337

T7

11

T9

60

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	45070	1			T5	510		T7	29		T9	182
values[1]	1344	1			T3	4		T5	16		T7	1
values[2]	1623	1			T5	15		T9	4		T15	5
values[3]	1737	1			T5	14		T7	2		T9	8
values[4]	1687	1			T5	12		T7	2		T9	3
values[5]	1740	1			T5	12		T9	4		T15	14
values[6]	1604	1			T5	11		T9	6		T15	8
values[7]	1734	1			T5	10		T7	4		T9	7
values[8]	11288	1			T5	95		T7	6		T9	15

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36103

1

T3

4

T7

44

T12

16

auto[1]

31724

1

T5

695

T9

235

T19

247

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

65287

1

T3

4

T5

664

T7

39

write

2540

1

T5

31

T7

5

T9

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

22678

1

T5

182

T7

22

T9

42

valids[0x1]

45149

1

T3

4

T5

513

T7

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1698	1			T5	20		T7	1		T9	1
internal_process_ops[0x5a]	1845	1			T5	16		T7	1		T9	4
internal_process_ops[0x05]	24125	1			T5	311		T7	5		T9	141
internal_process_ops[0x35]	1749	1			T5	13		T7	3		T9	4
internal_process_ops[0x15]	1793	1			T5	18		T7	2		T9	8
internal_process_ops[0x03]	1293	1			T5	3		T7	1		T14	6
internal_process_ops[0x0b]	1406	1			T3	4		T5	4		T15	7
internal_process_ops[0x3b]	1302	1			T5	1		T7	3		T9	1
internal_process_ops[0x6b]	1327	1			T5	4		T7	2		T12	4
internal_process_ops[0xbb]	1357	1			T5	4		T7	1		T9	1
internal_process_ops[0xeb]	1265	1			T5	3		T7	1		T9	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66597

1

T3

4

T5

686

T7

42

auto[1]

1230

1

T5

9

T7

2

T9

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65478

1

T3

4

T5

674

T7

42

auto[1]

2349

1

T5

21

T7

2

T9

9

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11973

1

T7

19

T12

4

T13

26

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7365

1

T15

72

T19

56

T25

16

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2579

1

T7

4

T12

2

T14

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2297

1

T7

4

T15

25

T19

15

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3105

1

T3

4

T7

4

T12

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2635

1

T7

3

T15

18

T19

21

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2510

1

T7

5

T12

6

T15

23

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2366

1

T15

11

T19

21

T25

11

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T15

2

T25

1

T27

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

70

1

T7

2

T15

1

T27

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

61

1

T15

2

T27

3

T116

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

82

1

T15

1

T26

1

T27

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

71

1

T19

1

T25

3

T26

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

77

1

T15

1

T19

2

T26

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

85

1

T27

1

T29

2

T67

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

78

1

T15

1

T19

2

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

86

1

T19

2

T25

1

T27

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

49

1

T25

1

T136

1

T137

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

68

1

T7

2

T27

3

T116

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

97

1

T19

2

T26

2

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

90

1

T26

1

T27

3

T30

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

72

1

T27

2

T29

2

T67

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

77

1

T7

1

T15

3

T19

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T15

1

T19

1

T25

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11057

1

T5

227

T9

129

T19

79

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8701

1

T5

239

T9

44

T19

27

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1698

1

T5

20

T9

7

T19

22

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1464

1

T5

36

T9

6

T19

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2161

1

T5

46

T9

7

T19

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1945

1

T5

39

T9

12

T19

29

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1854

1

T5

31

T9

14

T19

26

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1577

1

T5

26

T9

8

T19

19

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

77

1

T5

1

T19

3

T115

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

74

1

T36

1

T138

3

T139

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

78

1

T19

1

T24

1

T35

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

79

1

T5

6

T36

2

T66

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

91

1

T5

7

T19

5

T66

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

62

1

T9

3

T24

3

T35

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T5

2

T19

1

T36

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

77

1

T9

1

T36

4

T115

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

68

1

T5

1

T9

2

T66

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

64

1

T5

1

T35

1

T36

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

99

1

T5

3

T19

1

T66

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

73

1

T35

2

T36

1

T66

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

95

1

T5

2

T19

6

T66

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

86

1

T5

1

T36

2

T115

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

59

1

T5

6

T66

1

T115

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

90

1

T5

1

T9

2

T19

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4988	1			T7	8		T13	26		T15	47
auto[0]	values[0]	valids[0x1]	17660	1			T7	21		T12	4		T14	16
auto[0]	values[1]	valids[0x1]	755	1			T3	4		T7	1		T15	1
auto[0]	values[2]	valids[0x0]	644	1			T15	1		T19	4		T25	3
auto[0]	values[2]	valids[0x1]	339	1			T15	4		T25	1		T26	1
auto[0]	values[3]	valids[0x0]	660	1			T7	2		T12	6		T15	7
auto[0]	values[3]	valids[0x1]	373	1			T19	3		T26	10		T27	5
auto[0]	values[4]	valids[0x0]	641	1			T7	2		T12	2		T15	1
auto[0]	values[4]	valids[0x1]	382	1			T15	2		T26	4		T27	12
auto[0]	values[5]	valids[0x0]	740	1			T15	14		T19	6		T25	2
auto[0]	values[5]	valids[0x1]	328	1			T19	4		T25	2		T26	3
auto[0]	values[6]	valids[0x0]	645	1			T15	7		T19	2		T25	4
auto[0]	values[6]	valids[0x1]	338	1			T15	1		T19	3		T25	1
auto[0]	values[7]	valids[0x0]	636	1			T7	4		T15	5		T19	4
auto[0]	values[7]	valids[0x1]	368	1			T19	1		T25	1		T26	10
auto[0]	values[8]	valids[0x0]	4091	1			T7	6		T12	4		T15	27
auto[0]	values[8]	valids[0x1]	2515	1			T15	18		T19	16		T25	3
auto[1]	values[0]	valids[0x0]	4339	1			T5	90		T9	15		T19	45
auto[1]	values[0]	valids[0x1]	18083	1			T5	420		T9	167		T19	107
auto[1]	values[1]	valids[0x1]	589	1			T5	16		T9	6		T19	6
auto[1]	values[2]	valids[0x0]	383	1			T5	9		T19	3		T24	7
auto[1]	values[2]	valids[0x1]	257	1			T5	6		T9	4		T19	5
auto[1]	values[3]	valids[0x0]	426	1			T5	9		T9	3		T35	4
auto[1]	values[3]	valids[0x1]	278	1			T5	5		T9	5		T19	5
auto[1]	values[4]	valids[0x0]	437	1			T5	6		T9	3		T19	6
auto[1]	values[4]	valids[0x1]	227	1			T5	6		T19	2		T33	2
auto[1]	values[5]	valids[0x0]	390	1			T5	3		T9	2		T19	3
auto[1]	values[5]	valids[0x1]	282	1			T5	9		T9	2		T19	4
auto[1]	values[6]	valids[0x0]	367	1			T5	5		T9	2		T19	1
auto[1]	values[6]	valids[0x1]	254	1			T5	6		T9	4		T19	4
auto[1]	values[7]	valids[0x0]	443	1			T5	2		T9	6		T19	3
auto[1]	values[7]	valids[0x1]	287	1			T5	8		T9	1		T19	2
auto[1]	values[8]	valids[0x0]	2848	1			T5	58		T9	11		T19	40
auto[1]	values[8]	valids[0x1]	1834	1			T5	37		T9	4		T19	11