Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18246

1

T3

1

T5

138

T6

1

auto[1]

24454

1

T5

313

T7

6

T9

144

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15391

1

T3

1

T5

109

T6

1

auto[1]

27309

1

T5

342

T7

10

T9

153

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7170	1			T3	1		T5	118		T6	1
auto[524288:1048575]	4921	1			T5	108		T9	23		T12	1
auto[1048576:1572863]	5121	1			T5	54		T9	23		T12	3
auto[1572864:2097151]	5079	1			T5	19		T9	13		T12	2
auto[2097152:2621439]	5259	1			T5	19		T9	37		T12	2
auto[2621440:3145727]	4707	1			T5	36		T13	4		T15	23
auto[3145728:3670015]	5481	1			T5	13		T7	21		T9	19
auto[3670016:4194303]	4962	1			T5	84		T9	14		T13	4

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41792

1

T3

1

T5

447

T6

1

auto[1]

908

1

T5

4

T9

3

T15

10

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33872

1

T3

1

T5

266

T6

1

auto[1]

8828

1

T5

185

T7

17

T9

15

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1858	1			T3	1		T5	11		T6	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	735	1			T5	8		T9	3		T15	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1224	1			T5	5		T9	1		T12	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	465	1			T5	5		T15	3		T19	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1224	1			T5	17		T9	3		T12	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	500	1			T5	10		T9	2		T15	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1164	1			T5	5		T9	4		T12	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	399	1			T5	1		T9	4		T15	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1287	1			T5	3		T9	4		T12	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	490	1			T5	2		T15	3		T19	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1234	1			T5	2		T13	1		T15	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	518	1			T5	4		T19	10		T24	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1285	1			T5	5		T7	4		T9	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	485	1			T5	7		T9	2		T15	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1251	1			T5	9		T9	5		T13	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	469	1			T5	2		T9	1		T15	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	315	1			T5	3		T19	2		T45	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	146	1			T5	3		T19	2		T25	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	317	1			T5	11		T9	6		T24	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	155	1			T5	4		T9	4		T24	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	283	1			T5	2		T15	2		T19	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	130	1			T26	1		T36	1		T115	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	349	1			T5	7		T13	2		T15	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	143	1			T5	3		T25	1		T66	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	277	1			T5	5		T9	3		T19	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	131	1			T5	1		T9	2		T19	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	292	1			T5	1		T13	3		T15	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	136	1			T15	2		T35	2		T36	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	359	1			T5	1		T7	5		T19	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	155	1			T7	6		T19	1		T24	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	321	1			T5	1		T13	2		T15	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	149	1			T15	1		T19	2		T26	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	299	1			T5	4		T9	1		T19	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	3028	1			T5	64		T9	58		T19	16
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	212	1			T9	1		T15	1		T19	8
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1834	1			T9	11		T15	2		T19	31
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	193	1			T5	2		T9	1		T15	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2250	1			T5	23		T9	17		T15	30
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	208	1			T5	1		T9	1		T15	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2142	1			T5	2		T9	4		T15	11
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	218	1			T9	2		T19	2		T26	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2197	1			T9	26		T19	3		T26	9
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	222	1			T5	1		T15	2		T19	8
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1850	1			T5	1		T15	12		T19	33
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	250	1			T9	2		T15	2		T25	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2160	1			T9	12		T15	16		T25	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	247	1			T5	5		T9	1		T19	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1974	1			T5	67		T9	7		T19	22
auto[1]	auto[1]	auto[0:524287]	auto[0]	67	1			T5	1		T19	1		T66	6
auto[1]	auto[1]	auto[0:524287]	auto[1]	722	1			T5	24		T19	3		T66	30
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	56	1			T5	5		T24	1		T35	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	658	1			T5	78		T24	1		T35	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	56	1			T19	1		T36	1		T115	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	485	1			T19	3		T36	2		T115	22
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	75	1			T15	2		T66	1		T31	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	599	1			T15	4		T66	2		T31	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	47	1			T5	1		T66	1		T155	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	612	1			T5	7		T66	3		T155	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	53	1			T5	1		T155	1		T67	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	402	1			T5	26		T155	1		T67	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	83	1			T7	2		T19	2		T24	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	704	1			T7	4		T19	15		T24	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	65	1			T19	1		T25	1		T26	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	486	1			T19	1		T25	3		T26	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	14217	1			T3	1		T5	96		T6	1
auto[0]	auto[0]	auto[1]	371	1			T9	3		T15	2		T19	3
auto[0]	auto[1]	auto[0]	3541	1			T5	41		T7	11		T9	15
auto[0]	auto[1]	auto[1]	117	1			T5	1		T15	1		T19	1
auto[1]	auto[0]	auto[0]	18963	1			T5	168		T9	144		T15	77
auto[1]	auto[0]	auto[1]	321	1			T5	2		T15	5		T19	4
auto[1]	auto[1]	auto[0]	5071	1			T5	142		T7	6		T15	4
auto[1]	auto[1]	auto[1]	99	1			T5	1		T15	2		T19	2