Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20792

1

T3

4

T7

34

T12

16

auto[1]

15311

1

T7

10

T15

134

T19

120

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4257	1			T13	26		T15	31		T45	22
values[1]	4930	1			T19	116		T78	10		T26	48
values[2]	4121	1			T15	24		T19	108		T25	20
values[3]	5138	1			T3	4		T15	40		T19	20
values[4]	3895	1			T14	16		T15	112		T19	32
values[5]	4516	1			T12	16		T26	47		T27	40
values[6]	5208	1			T7	44		T15	50		T32	16
values[7]	4038	1			T15	20		T26	82		T27	80

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3995	1			T3	4		T14	16		T19	104
values[1]	4077	1			T25	20		T26	21		T27	81
values[2]	4873	1			T7	20		T15	23		T19	43
values[3]	4996	1			T15	20		T25	23		T26	73
values[4]	4792	1			T15	65		T32	16		T19	106
values[5]	4187	1			T7	24		T12	16		T13	26
values[6]	4550	1			T15	67		T19	26		T25	21
values[7]	4633	1			T15	31		T19	23		T78	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	294	1			T30	64		T136	12		T128	12
auto[0]	values[0]	values[1]	281	1			T26	6		T27	14		T29	14
auto[0]	values[0]	values[2]	488	1			T26	14		T29	22		T30	22
auto[0]	values[0]	values[3]	242	1			T25	13		T116	13		T31	9
auto[0]	values[0]	values[4]	317	1			T26	6		T116	13		T161	25
auto[0]	values[0]	values[5]	228	1			T13	26		T45	22		T29	18
auto[0]	values[0]	values[6]	284	1			T25	10		T31	11		T156	7
auto[0]	values[0]	values[7]	309	1			T15	24		T31	14		T69	22
auto[0]	values[1]	values[0]	386	1			T19	22		T31	13		T156	55
auto[0]	values[1]	values[1]	142	1			T29	24		T159	7		T152	26
auto[0]	values[1]	values[2]	400	1			T31	9		T67	27		T69	35
auto[0]	values[1]	values[3]	457	1			T26	9		T67	16		T168	11
auto[0]	values[1]	values[4]	410	1			T19	62		T26	6		T30	7
auto[0]	values[1]	values[5]	165	1			T69	9		T147	15		T20	12
auto[0]	values[1]	values[6]	508	1			T31	47		T156	11		T69	5
auto[0]	values[1]	values[7]	321	1			T78	10		T136	12		T156	17
auto[0]	values[2]	values[0]	274	1			T19	15		T172	14		T116	13
auto[0]	values[2]	values[1]	331	1			T27	41		T166	2		T30	7
auto[0]	values[2]	values[2]	249	1			T19	26		T25	11		T67	43
auto[0]	values[2]	values[3]	268	1			T148	12		T69	12		T187	10
auto[0]	values[2]	values[4]	246	1			T188	8		T148	8		T146	34
auto[0]	values[2]	values[5]	392	1			T15	9		T26	17		T27	16
auto[0]	values[2]	values[6]	292	1			T27	11		T189	8		T152	26
auto[0]	values[2]	values[7]	229	1			T19	15		T67	60		T159	20
auto[0]	values[3]	values[0]	439	1			T3	4		T19	16		T26	12
auto[0]	values[3]	values[1]	345	1			T30	14		T136	9		T69	23
auto[0]	values[3]	values[2]	373	1			T190	2		T27	24		T31	11
auto[0]	values[3]	values[3]	462	1			T148	22		T128	15		T152	16
auto[0]	values[3]	values[4]	263	1			T128	11		T152	11		T191	4
auto[0]	values[3]	values[5]	322	1			T69	14		T128	9		T192	2
auto[0]	values[3]	values[6]	398	1			T15	24		T163	9		T193	16
auto[0]	values[3]	values[7]	463	1			T27	30		T116	15		T29	13
auto[0]	values[4]	values[0]	206	1			T14	16		T29	9		T136	7
auto[0]	values[4]	values[1]	164	1			T184	12		T153	23		T160	12
auto[0]	values[4]	values[2]	224	1			T67	15		T128	14		T159	10
auto[0]	values[4]	values[3]	275	1			T136	17		T168	17		T149	22
auto[0]	values[4]	values[4]	339	1			T15	10		T19	9		T31	7
auto[0]	values[4]	values[5]	432	1			T15	28		T182	10		T26	17
auto[0]	values[4]	values[6]	187	1			T194	2		T20	11		T183	16
auto[0]	values[4]	values[7]	328	1			T156	12		T69	12		T195	2
auto[0]	values[5]	values[0]	224	1			T69	14		T168	11		T196	17
auto[0]	values[5]	values[1]	221	1			T165	24		T197	72		T67	15
auto[0]	values[5]	values[2]	272	1			T30	16		T186	14		T136	13
auto[0]	values[5]	values[3]	409	1			T26	17		T27	16		T116	14
auto[0]	values[5]	values[4]	429	1			T26	11		T185	22		T198	16
auto[0]	values[5]	values[5]	375	1			T12	16		T27	9		T31	9
auto[0]	values[5]	values[6]	292	1			T136	14		T199	2		T160	13
auto[0]	values[5]	values[7]	404	1			T116	7		T29	17		T200	10
auto[0]	values[6]	values[0]	260	1			T25	17		T27	10		T136	8
auto[0]	values[6]	values[1]	283	1			T25	12		T31	11		T168	12
auto[0]	values[6]	values[2]	506	1			T7	13		T15	16		T201	14
auto[0]	values[6]	values[3]	520	1			T26	12		T31	22		T67	119
auto[0]	values[6]	values[4]	563	1			T32	16		T156	6		T161	11
auto[0]	values[6]	values[5]	362	1			T7	21		T27	25		T29	27
auto[0]	values[6]	values[6]	310	1			T15	21		T19	17		T27	11
auto[0]	values[6]	values[7]	402	1			T29	11		T148	14		T168	13
auto[0]	values[7]	values[0]	176	1			T26	9		T67	8		T152	24
auto[0]	values[7]	values[1]	264	1			T161	8		T153	17		T147	21
auto[0]	values[7]	values[2]	236	1			T26	7		T27	12		T29	22
auto[0]	values[7]	values[3]	359	1			T15	11		T136	17		T152	12
auto[0]	values[7]	values[4]	391	1			T26	20		T27	15		T67	8
auto[0]	values[7]	values[5]	262	1			T116	12		T30	9		T69	19
auto[0]	values[7]	values[6]	231	1			T29	8		T30	9		T161	11
auto[0]	values[7]	values[7]	308	1			T26	9		T27	8		T29	18
auto[1]	values[0]	values[0]	158	1			T30	9		T136	8		T128	8
auto[1]	values[0]	values[1]	216	1			T26	15		T27	6		T29	8
auto[1]	values[0]	values[2]	215	1			T26	9		T29	18		T30	3
auto[1]	values[0]	values[3]	245	1			T25	10		T116	7		T31	11
auto[1]	values[0]	values[4]	293	1			T26	14		T116	9		T161	52
auto[1]	values[0]	values[5]	170	1			T29	5		T202	9		T130	8
auto[1]	values[0]	values[6]	326	1			T25	11		T31	9		T156	42
auto[1]	values[0]	values[7]	191	1			T15	7		T31	6		T69	20
auto[1]	values[1]	values[0]	216	1			T19	20		T31	7		T156	7
auto[1]	values[1]	values[1]	124	1			T29	22		T159	13		T152	19
auto[1]	values[1]	values[2]	540	1			T31	21		T67	8		T69	12
auto[1]	values[1]	values[3]	311	1			T26	17		T67	12		T168	10
auto[1]	values[1]	values[4]	345	1			T19	12		T26	16		T30	13
auto[1]	values[1]	values[5]	109	1			T69	11		T147	5		T20	10
auto[1]	values[1]	values[6]	314	1			T31	18		T156	17		T69	15
auto[1]	values[1]	values[7]	182	1			T136	8		T156	4		T69	9
auto[1]	values[2]	values[0]	184	1			T19	27		T116	13		T30	46
auto[1]	values[2]	values[1]	552	1			T27	20		T30	13		T156	17
auto[1]	values[2]	values[2]	215	1			T19	17		T25	9		T67	61
auto[1]	values[2]	values[3]	222	1			T148	10		T69	8		T152	9
auto[1]	values[2]	values[4]	101	1			T148	14		T69	8		T163	12
auto[1]	values[2]	values[5]	289	1			T15	15		T26	11		T27	4
auto[1]	values[2]	values[6]	169	1			T27	9		T152	19		T137	10
auto[1]	values[2]	values[7]	108	1			T19	8		T67	4		T159	8
auto[1]	values[3]	values[0]	294	1			T19	4		T26	8		T167	26
auto[1]	values[3]	values[1]	368	1			T30	9		T136	23		T69	53
auto[1]	values[3]	values[2]	337	1			T27	18		T31	9		T148	22
auto[1]	values[3]	values[3]	253	1			T148	18		T128	8		T152	6
auto[1]	values[3]	values[4]	171	1			T128	9		T203	2		T152	15
auto[1]	values[3]	values[5]	221	1			T69	6		T128	13		T160	9
auto[1]	values[3]	values[6]	186	1			T15	16		T163	11		T204	9
auto[1]	values[3]	values[7]	243	1			T27	6		T116	5		T29	10
auto[1]	values[4]	values[0]	187	1			T29	11		T136	50		T183	5
auto[1]	values[4]	values[1]	99	1			T153	7		T160	11		T178	9
auto[1]	values[4]	values[2]	244	1			T67	5		T128	6		T159	10
auto[1]	values[4]	values[3]	277	1			T136	3		T168	11		T149	18
auto[1]	values[4]	values[4]	231	1			T15	55		T19	23		T31	14
auto[1]	values[4]	values[5]	166	1			T15	19		T26	9		T29	9
auto[1]	values[4]	values[6]	118	1			T20	10		T183	4		T169	21
auto[1]	values[4]	values[7]	418	1			T156	156		T69	8		T202	12
auto[1]	values[5]	values[0]	176	1			T69	10		T168	9		T196	8
auto[1]	values[5]	values[1]	200	1			T67	5		T136	7		T161	14
auto[1]	values[5]	values[2]	117	1			T30	4		T136	7		T128	10
auto[1]	values[5]	values[3]	305	1			T26	10		T27	4		T116	9
auto[1]	values[5]	values[4]	206	1			T26	9		T169	12		T205	3
auto[1]	values[5]	values[5]	324	1			T27	11		T31	11		T149	125
auto[1]	values[5]	values[6]	238	1			T136	6		T160	7		T149	20
auto[1]	values[5]	values[7]	324	1			T116	13		T29	6		T67	18
auto[1]	values[6]	values[0]	248	1			T25	6		T27	10		T136	12
auto[1]	values[6]	values[1]	231	1			T25	8		T31	9		T168	8
auto[1]	values[6]	values[2]	276	1			T7	7		T15	7		T31	12
auto[1]	values[6]	values[3]	205	1			T26	8		T31	8		T67	9
auto[1]	values[6]	values[4]	193	1			T156	25		T161	9		T152	4
auto[1]	values[6]	values[5]	246	1			T7	3		T27	29		T29	17
auto[1]	values[6]	values[6]	368	1			T15	6		T19	9		T27	9
auto[1]	values[6]	values[7]	235	1			T29	12		T148	7		T168	7
auto[1]	values[7]	values[0]	273	1			T26	11		T67	50		T152	8
auto[1]	values[7]	values[1]	256	1			T161	28		T153	16		T147	4
auto[1]	values[7]	values[2]	181	1			T26	13		T27	14		T28	12
auto[1]	values[7]	values[3]	186	1			T15	9		T136	3		T152	10
auto[1]	values[7]	values[4]	294	1			T26	2		T27	19		T67	29
auto[1]	values[7]	values[5]	124	1			T116	9		T30	12		T69	21
auto[1]	values[7]	values[6]	329	1			T29	12		T30	12		T161	9
auto[1]	values[7]	values[7]	168	1			T26	11		T27	12		T29	3