Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	510	1			T7	1		T15	5		T19	5
auto[ReadAddrCrossIntoMailbox]	401	1			T15	2		T19	3		T25	4
auto[ReadAddrCrossOutOfMailbox]	427	1			T15	4		T19	5		T25	3
auto[ReadAddrCrossAllMailbox]	274	1			T15	2		T19	8		T25	1
auto[ReadAddrOutsideMailbox]	4220	1			T3	4		T7	7		T12	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2879

1

T3

2

T7

3

T12

5

auto[1]

2953

1

T3

2

T7

5

T12

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	976	1			T7	1		T14	6		T15	8
read_ops[0x0b]	1026	1			T3	4		T15	7		T19	8
read_ops[0x3b]	965	1			T7	3		T15	6		T19	4
read_ops[0x6b]	957	1			T7	2		T12	4		T15	14
read_ops[0xbb]	978	1			T7	1		T12	6		T15	6
read_ops[0xeb]	930	1			T7	1		T15	6		T19	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T29	2		T31	1		T67	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T19	1		T25	2		T27	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T27	1		T172	1		T31	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T26	1		T172	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	42	1			T15	1		T26	1		T29	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T15	1		T26	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T172	1		T30	1		T31	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T25	1		T27	1		T172	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	370	1			T14	3		T15	3		T19	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	332	1			T7	1		T14	3		T15	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T27	1		T31	3		T162	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	51	1			T29	1		T30	1		T148	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T29	2		T30	4		T31	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	38	1			T26	1		T29	1		T30	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T19	2		T27	1		T29	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T26	1		T27	1		T29	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T30	1		T31	1		T156	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T19	3		T27	1		T29	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	361	1			T3	2		T15	1		T25	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	376	1			T3	2		T15	6		T19	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T29	1		T30	1		T31	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T7	1		T15	1		T25	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T25	2		T26	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T15	1		T31	1		T69	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T25	2		T30	1		T67	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T31	1		T136	1		T69	4
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T19	1		T29	2		T30	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T15	1		T31	1		T69	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	354	1			T7	1		T15	1		T19	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	362	1			T7	1		T15	2		T25	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T27	1		T31	1		T136	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	51	1			T15	1		T19	1		T27	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T116	1		T67	2		T161	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T19	1		T27	2		T67	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T15	2		T19	1		T27	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T26	1		T30	1		T67	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T161	1		T152	3		T149	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T19	1		T116	1		T136	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T12	2		T15	7		T19	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	386	1			T7	2		T12	2		T15	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T25	2		T27	1		T29	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T15	1		T26	1		T27	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T19	1		T30	1		T186	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T186	1		T67	1		T136	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T19	2		T186	1		T67	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T30	3		T186	1		T67	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	31	1			T19	1		T27	1		T30	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T19	2		T186	1		T67	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	354	1			T7	1		T12	3		T15	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	370	1			T12	3		T25	2		T182	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T15	2		T19	3		T186	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T25	1		T116	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T15	1		T186	1		T67	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	42	1			T19	1		T25	2		T27	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	52	1			T186	1		T67	1		T148	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T25	1		T186	1		T31	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T15	1		T69	1		T168	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T31	1		T136	1		T20	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	309	1			T7	1		T15	2		T19	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	342	1			T19	2		T25	1		T26	9