Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6981052	1			T1	1		T2	1		T3	1
all_pins[1]	6981052	1			T1	1		T2	1		T3	1
all_pins[2]	6981052	1			T1	1		T2	1		T3	1
all_pins[3]	6981052	1			T1	1		T2	1		T3	1
all_pins[4]	6981052	1			T1	1		T2	1		T3	1
all_pins[5]	6981052	1			T1	1		T2	1		T3	1
all_pins[6]	6981052	1			T1	1		T2	1		T3	1
all_pins[7]	6981052	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	55840765	1			T1	8		T2	8		T3	8
values[0x1]	7651	1			T19	615		T24	39		T44	4
transitions[0x0=>0x1]	6689	1			T19	599		T24	30		T44	3
transitions[0x1=>0x0]	6700	1			T19	599		T24	31		T44	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6980655	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	397	1			T19	195		T24	4		T35	1
all_pins[0]	transitions[0x0=>0x1]	335	1			T19	193		T24	1		T36	1
all_pins[0]	transitions[0x1=>0x0]	158	1			T19	1		T24	3		T36	6
all_pins[1]	values[0x0]	6980832	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	220	1			T19	3		T24	6		T35	1
all_pins[1]	transitions[0x0=>0x1]	163	1			T24	4		T36	5		T115	2
all_pins[1]	transitions[0x1=>0x0]	170	1			T19	10		T24	4		T44	1
all_pins[2]	values[0x0]	6980825	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	227	1			T19	13		T24	6		T44	1
all_pins[2]	transitions[0x0=>0x1]	163	1			T19	8		T24	4		T44	1
all_pins[2]	transitions[0x1=>0x0]	180	1			T19	5		T24	5		T35	2
all_pins[3]	values[0x0]	6980808	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	244	1			T19	10		T24	7		T35	2
all_pins[3]	transitions[0x0=>0x1]	201	1			T19	7		T24	7		T36	7
all_pins[3]	transitions[0x1=>0x0]	159	1			T19	1		T24	2		T44	1
all_pins[4]	values[0x0]	6980850	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	202	1			T19	4		T24	2		T44	1
all_pins[4]	transitions[0x0=>0x1]	158	1			T19	3		T24	2		T44	1
all_pins[4]	transitions[0x1=>0x0]	2137	1			T19	380		T24	5		T35	1073
all_pins[5]	values[0x0]	6978871	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	2181	1			T19	381		T24	5		T35	1074
all_pins[5]	transitions[0x0=>0x1]	1611	1			T19	380		T24	5		T35	1074
all_pins[5]	transitions[0x1=>0x0]	3375	1			T19	4		T24	4		T44	1
all_pins[6]	values[0x0]	6977107	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	3945	1			T19	5		T24	4		T44	1
all_pins[6]	transitions[0x0=>0x1]	3886	1			T19	5		T24	3		T35	2
all_pins[6]	transitions[0x1=>0x0]	176	1			T19	4		T24	4		T35	2
all_pins[7]	values[0x0]	6980817	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	235	1			T19	4		T24	5		T44	1
all_pins[7]	transitions[0x0=>0x1]	172	1			T19	3		T24	4		T44	1
all_pins[7]	transitions[0x1=>0x0]	345	1			T19	194		T24	4		T35	1