Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4962	1			T15	20		T25	23		T26	27
values[1]	4522	1			T3	4		T15	78		T19	20
values[2]	4560	1			T7	20		T15	50		T19	72
values[3]	5195	1			T12	16		T15	89		T25	21
values[4]	4432	1			T7	24		T13	26		T15	20
values[5]	4178	1			T14	16		T15	20		T19	106
values[6]	3778	1			T19	20		T26	46		T27	61
values[7]	4476	1			T32	16		T19	22		T25	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5161	1			T12	16		T15	31		T19	40
values[1]	4560	1			T7	20		T15	112		T19	32
values[2]	4257	1			T15	20		T19	64		T25	20
values[3]	3939	1			T7	24		T14	16		T15	20
values[4]	4254	1			T3	4		T15	27		T25	23
values[5]	4535	1			T19	46		T25	23		T26	20
values[6]	5063	1			T13	26		T15	23		T32	16
values[7]	4334	1			T15	44		T78	10		T26	23

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35478

1

T3

4

T7

42

T12

16

auto[1]

625

1

T7

2

T15

5

T19

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	613	1			T136	20		T206	22		T61	26
auto[0]	values[0]	values[1]	963	1			T29	23		T67	20		T136	20
auto[0]	values[0]	values[2]	565	1			T26	24		T27	26		T167	26
auto[0]	values[0]	values[3]	553	1			T15	19		T116	20		T156	31
auto[0]	values[0]	values[4]	545	1			T27	20		T166	2		T201	14
auto[0]	values[0]	values[5]	740	1			T25	23		T207	22		T159	72
auto[0]	values[0]	values[6]	578	1			T116	26		T150	22		T30	19
auto[0]	values[0]	values[7]	333	1			T116	22		T30	20		T67	34
auto[0]	values[1]	values[0]	610	1			T15	31		T26	20		T67	63
auto[0]	values[1]	values[1]	597	1			T15	27		T45	22		T26	20
auto[0]	values[1]	values[2]	466	1			T15	20		T29	40		T20	20
auto[0]	values[1]	values[3]	394	1			T29	22		T69	24		T128	20
auto[0]	values[1]	values[4]	477	1			T3	4		T26	22		T148	41
auto[0]	values[1]	values[5]	691	1			T161	22		T152	25		T195	2
auto[0]	values[1]	values[6]	705	1			T19	20		T31	29		T69	41
auto[0]	values[1]	values[7]	499	1			T27	20		T31	20		T152	20
auto[0]	values[2]	values[0]	596	1			T31	41		T208	2		T178	20
auto[0]	values[2]	values[1]	505	1			T7	18		T25	19		T116	20
auto[0]	values[2]	values[2]	649	1			T27	40		T197	72		T148	20
auto[0]	values[2]	values[3]	630	1			T26	22		T27	22		T187	10
auto[0]	values[2]	values[4]	478	1			T15	24		T190	2		T29	22
auto[0]	values[2]	values[5]	559	1			T19	45		T27	23		T29	19
auto[0]	values[2]	values[6]	571	1			T15	23		T19	26		T168	20
auto[0]	values[2]	values[7]	503	1			T29	23		T31	21		T136	20
auto[0]	values[3]	values[0]	775	1			T12	16		T27	73		T116	20
auto[0]	values[3]	values[1]	641	1			T15	64		T25	20		T209	20
auto[0]	values[3]	values[2]	752	1			T116	21		T29	20		T31	30
auto[0]	values[3]	values[3]	563	1			T29	26		T136	20		T128	20
auto[0]	values[3]	values[4]	622	1			T29	20		T30	68		T152	26
auto[0]	values[3]	values[5]	448	1			T30	20		T31	20		T148	21
auto[0]	values[3]	values[6]	805	1			T26	28		T69	20		T128	20
auto[0]	values[3]	values[7]	504	1			T15	24		T27	35		T186	14
auto[0]	values[4]	values[0]	633	1			T19	17		T148	20		T136	19
auto[0]	values[4]	values[1]	489	1			T26	20		T30	62		T200	10
auto[0]	values[4]	values[2]	531	1			T19	42		T25	20		T29	20
auto[0]	values[4]	values[3]	435	1			T7	24		T69	34		T184	12
auto[0]	values[4]	values[4]	432	1			T26	20		T29	20		T161	36
auto[0]	values[4]	values[5]	509	1			T29	23		T67	77		T69	69
auto[0]	values[4]	values[6]	585	1			T13	26		T27	30		T28	10
auto[0]	values[4]	values[7]	737	1			T15	20		T31	20		T67	37
auto[0]	values[5]	values[0]	809	1			T26	26		T30	20		T156	49
auto[0]	values[5]	values[1]	344	1			T15	20		T19	31		T26	20
auto[0]	values[5]	values[2]	313	1			T67	27		T148	21		T69	20
auto[0]	values[5]	values[3]	433	1			T14	16		T19	72		T182	10
auto[0]	values[5]	values[4]	411	1			T165	24		T67	20		T173	26
auto[0]	values[5]	values[5]	457	1			T69	20		T210	4		T153	20
auto[0]	values[5]	values[6]	734	1			T26	20		T31	22		T67	75
auto[0]	values[5]	values[7]	592	1			T78	10		T26	23		T30	25
auto[0]	values[6]	values[0]	468	1			T19	20		T26	20		T27	33
auto[0]	values[6]	values[1]	368	1			T26	26		T27	26		T148	20
auto[0]	values[6]	values[2]	430	1			T148	21		T136	20		T20	42
auto[0]	values[6]	values[3]	403	1			T172	14		T29	20		T136	20
auto[0]	values[6]	values[4]	821	1			T116	23		T67	56		T136	18
auto[0]	values[6]	values[5]	410	1			T156	20		T149	33		T202	40
auto[0]	values[6]	values[6]	382	1			T30	26		T174	14		T153	20
auto[0]	values[6]	values[7]	420	1			T30	20		T31	20		T161	16
auto[0]	values[7]	values[0]	563	1			T67	30		T156	62		T152	21
auto[0]	values[7]	values[1]	573	1			T27	19		T116	20		T168	20
auto[0]	values[7]	values[2]	472	1			T19	22		T27	19		T211	6
auto[0]	values[7]	values[3]	471	1			T29	20		T31	20		T161	20
auto[0]	values[7]	values[4]	394	1			T25	23		T69	27		T183	20
auto[0]	values[7]	values[5]	640	1			T26	20		T29	21		T69	20
auto[0]	values[7]	values[6]	614	1			T32	16		T156	94		T153	20
auto[0]	values[7]	values[7]	675	1			T188	8		T67	43		T156	20
auto[1]	values[0]	values[0]	3	1			T212	2		T213	1		-	-
auto[1]	values[0]	values[1]	15	1			T137	1		T178	1		T170	2
auto[1]	values[0]	values[2]	10	1			T26	3		T69	1		T152	1
auto[1]	values[0]	values[3]	12	1			T15	1		T161	3		T214	2
auto[1]	values[0]	values[4]	7	1			T20	1		T130	4		T215	2
auto[1]	values[0]	values[5]	10	1			T159	1		T216	3		T176	1
auto[1]	values[0]	values[6]	12	1			T30	1		T31	1		T160	2
auto[1]	values[0]	values[7]	3	1			T67	1		T215	1		T217	1
auto[1]	values[1]	values[0]	9	1			T67	1		T136	2		T218	1
auto[1]	values[1]	values[1]	7	1			T29	2		T137	1		T176	1
auto[1]	values[1]	values[2]	9	1			T29	1		T160	5		T219	1
auto[1]	values[1]	values[3]	7	1			T37	2		T176	2		T220	3
auto[1]	values[1]	values[4]	10	1			T148	1		T153	2		T196	1
auto[1]	values[1]	values[5]	18	1			T152	3		T169	1		T196	1
auto[1]	values[1]	values[6]	11	1			T31	1		T37	2		T221	3
auto[1]	values[1]	values[7]	12	1			T202	1		T170	3		T204	1
auto[1]	values[2]	values[0]	7	1			T205	2		T170	2		T196	1
auto[1]	values[2]	values[1]	7	1			T7	2		T25	1		T149	1
auto[1]	values[2]	values[2]	15	1			T148	2		T214	5		T218	5
auto[1]	values[2]	values[3]	8	1			T222	2		T169	1		T221	4
auto[1]	values[2]	values[4]	10	1			T15	3		T29	1		T69	1
auto[1]	values[2]	values[5]	10	1			T19	1		T29	1		T20	1
auto[1]	values[2]	values[6]	8	1			T170	1		T171	1		T130	1
auto[1]	values[2]	values[7]	4	1			T196	1		T223	3		-	-
auto[1]	values[3]	values[0]	14	1			T27	1		T67	1		T158	4
auto[1]	values[3]	values[1]	15	1			T15	1		T25	1		T153	2
auto[1]	values[3]	values[2]	7	1			T128	1		T216	1		T176	2
auto[1]	values[3]	values[3]	7	1			T159	2		T202	2		T216	3
auto[1]	values[3]	values[4]	15	1			T169	5		T170	1		T224	1
auto[1]	values[3]	values[5]	4	1			T31	1		T148	1		T158	2
auto[1]	values[3]	values[6]	16	1			T225	5		T226	1		T227	1
auto[1]	values[3]	values[7]	7	1			T27	1		T149	2		T170	1
auto[1]	values[4]	values[0]	19	1			T19	3		T136	1		T152	4
auto[1]	values[4]	values[1]	13	1			T30	1		T137	1		T228	2
auto[1]	values[4]	values[2]	9	1			T183	2		T171	2		T196	1
auto[1]	values[4]	values[3]	7	1			T69	2		T204	1		T216	1
auto[1]	values[4]	values[4]	5	1			T229	2		T230	1		T231	2
auto[1]	values[4]	values[5]	5	1			T153	2		T130	2		T76	1
auto[1]	values[4]	values[6]	8	1			T27	1		T28	2		T128	1
auto[1]	values[4]	values[7]	15	1			T136	2		T159	1		T223	1
auto[1]	values[5]	values[0]	14	1			T30	1		T128	2		T159	1
auto[1]	values[5]	values[1]	7	1			T19	1		T26	1		T204	3
auto[1]	values[5]	values[2]	8	1			T67	1		T128	1		T176	2
auto[1]	values[5]	values[3]	8	1			T19	2		T31	2		T159	1
auto[1]	values[5]	values[4]	7	1			T232	2		T216	4		T233	1
auto[1]	values[5]	values[5]	10	1			T170	1		T130	2		T234	3
auto[1]	values[5]	values[6]	19	1			T31	2		T67	1		T153	1
auto[1]	values[5]	values[7]	12	1			T156	1		T152	3		T223	2
auto[1]	values[6]	values[0]	17	1			T27	2		T235	3		T234	3
auto[1]	values[6]	values[1]	5	1			T137	2		T40	3		-	-
auto[1]	values[6]	values[2]	6	1			T178	1		T214	1		T37	3
auto[1]	values[6]	values[3]	5	1			T29	1		T236	2		T131	2
auto[1]	values[6]	values[4]	17	1			T67	2		T136	2		T153	4
auto[1]	values[6]	values[5]	9	1			T202	1		T130	2		T176	1
auto[1]	values[6]	values[6]	8	1			T30	1		T149	2		T130	1
auto[1]	values[6]	values[7]	9	1			T161	4		T153	1		T160	1
auto[1]	values[7]	values[0]	11	1			T152	1		T234	1		T230	4
auto[1]	values[7]	values[1]	11	1			T27	1		T116	1		T161	3
auto[1]	values[7]	values[2]	15	1			T27	1		T152	1		T237	12
auto[1]	values[7]	values[3]	3	1			T152	1		T230	1		T238	1
auto[1]	values[7]	values[4]	3	1			T239	2		T240	1		-	-
auto[1]	values[7]	values[5]	15	1			T29	2		T128	1		T161	2
auto[1]	values[7]	values[6]	7	1			T215	3		T238	1		T241	2
auto[1]	values[7]	values[7]	9	1			T169	1		T234	1		T158	1