SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 181 | 1 | T33 | 5 | T118 | 2 | T119 | 1 | ||||
auto[1] | 160 | 1 | T33 | 4 | T118 | 2 | T119 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
read_ops[0x03] | 42 | 1 | T242 | 4 | T243 | 2 | T244 | 8 | ||||
read_ops[0x0b] | 29 | 1 | T33 | 6 | T245 | 2 | T180 | 2 | ||||
read_ops[0x3b] | 54 | 1 | T245 | 3 | T64 | 7 | T243 | 1 | ||||
read_ops[0x6b] | 75 | 1 | T33 | 1 | T118 | 4 | T181 | 4 | ||||
read_ops[0xbb] | 75 | 1 | T33 | 2 | T119 | 2 | T181 | 2 | ||||
read_ops[0xeb] | 66 | 1 | T245 | 2 | T180 | 2 | T242 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |