Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2524

1

T1

19

T2

2

T4

25

auto[1]

2540

1

T1

19

T4

22

T5

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2708

1

T5

14

T7

19

T9

2

auto[1]

2356

1

T1

38

T2

2

T4

47

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4022

1

T1

38

T2

2

T4

47

auto[1]

1042

1

T5

6

T7

8

T10

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1040	1			T1	8		T2	1		T4	11
valid[1]	1036	1			T1	5		T4	11		T5	1
valid[2]	978	1			T1	9		T4	7		T5	4
valid[3]	989	1			T1	8		T2	1		T4	13
valid[4]	1021	1			T1	8		T4	5		T5	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	193	1			T5	2		T7	2		T10	1
auto[0]	auto[0]	valid[0]	auto[1]	236	1			T1	6		T2	1		T4	4
auto[0]	auto[0]	valid[1]	auto[0]	187	1			T7	1		T10	1		T19	3
auto[0]	auto[0]	valid[1]	auto[1]	229	1			T1	4		T4	8		T16	1
auto[0]	auto[0]	valid[2]	auto[0]	167	1			T7	1		T9	2		T10	3
auto[0]	auto[0]	valid[2]	auto[1]	203	1			T1	3		T4	4		T17	3
auto[0]	auto[0]	valid[3]	auto[0]	166	1			T7	1		T10	1		T15	1
auto[0]	auto[0]	valid[3]	auto[1]	242	1			T1	4		T2	1		T4	4
auto[0]	auto[0]	valid[4]	auto[0]	165	1			T7	1		T10	2		T19	2
auto[0]	auto[0]	valid[4]	auto[1]	241	1			T1	2		T4	5		T16	1
auto[0]	auto[1]	valid[0]	auto[0]	157	1			T5	1		T7	1		T10	1
auto[0]	auto[1]	valid[0]	auto[1]	242	1			T1	2		T4	7		T9	2
auto[0]	auto[1]	valid[1]	auto[0]	156	1			T7	2		T19	1		T24	2
auto[0]	auto[1]	valid[1]	auto[1]	263	1			T1	1		T4	3		T16	1
auto[0]	auto[1]	valid[2]	auto[0]	170	1			T5	2		T19	2		T24	2
auto[0]	auto[1]	valid[2]	auto[1]	234	1			T1	6		T4	3		T16	1
auto[0]	auto[1]	valid[3]	auto[0]	155	1			T5	1		T7	1		T10	1
auto[0]	auto[1]	valid[3]	auto[1]	233	1			T1	4		T4	9		T17	4
auto[0]	auto[1]	valid[4]	auto[0]	150	1			T5	2		T7	1		T10	4
auto[0]	auto[1]	valid[4]	auto[1]	233	1			T1	6		T17	5		T77	1
auto[1]	auto[0]	valid[0]	auto[0]	98	1			T10	1		T24	2		T26	1
auto[1]	auto[0]	valid[1]	auto[0]	97	1			T5	1		T24	1		T25	1
auto[1]	auto[0]	valid[2]	auto[0]	88	1			T19	2		T26	1		T35	1
auto[1]	auto[0]	valid[3]	auto[0]	92	1			T7	2		T25	1		T35	1
auto[1]	auto[0]	valid[4]	auto[0]	120	1			T5	1		T7	1		T19	1
auto[1]	auto[1]	valid[0]	auto[0]	114	1			T7	2		T19	1		T24	1
auto[1]	auto[1]	valid[1]	auto[0]	104	1			T7	1		T10	2		T19	2
auto[1]	auto[1]	valid[2]	auto[0]	116	1			T5	2		T7	2		T19	1
auto[1]	auto[1]	valid[3]	auto[0]	101	1			T24	1		T35	1		T36	1
auto[1]	auto[1]	valid[4]	auto[0]	112	1			T5	2		T10	1		T24	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal