Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68701

1

T5

250

T7

594

T9

67

auto[1]

24448

1

T1

541

T2

35

T4

549

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68173

1

T1

541

T2

35

T4

549

auto[1]

24976

1

T5

80

T7

218

T9

25

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	47889	1			T1	288		T2	18		T4	277
others[1]	7859	1			T1	43		T2	6		T4	49
others[2]	7883	1			T1	34		T2	2		T4	50
others[3]	9028	1			T1	49		T2	2		T4	53
interest[1]	5114	1			T1	30		T2	2		T4	32
interest[4]	31296	1			T1	202		T2	15		T4	179
interest[64]	15376	1			T1	97		T2	5		T4	88

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	22240	1			T5	87		T7	199		T9	25
auto[0]	auto[0]	others[1]	3784	1			T5	13		T7	24		T9	1
auto[0]	auto[0]	others[2]	3722	1			T5	21		T7	32		T9	4
auto[0]	auto[0]	others[3]	4215	1			T5	20		T7	38		T9	6
auto[0]	auto[0]	interest[1]	2409	1			T5	6		T7	20		T9	2
auto[0]	auto[0]	interest[4]	14475	1			T5	53		T7	141		T9	13
auto[0]	auto[0]	interest[64]	7355	1			T5	23		T7	63		T9	4
auto[0]	auto[1]	others[0]	12832	1			T1	288		T2	18		T4	277
auto[0]	auto[1]	others[1]	1985	1			T1	43		T2	6		T4	49
auto[0]	auto[1]	others[2]	2040	1			T1	34		T2	2		T4	50
auto[0]	auto[1]	others[3]	2338	1			T1	49		T2	2		T4	53
auto[0]	auto[1]	interest[1]	1333	1			T1	30		T2	2		T4	32
auto[0]	auto[1]	interest[4]	8492	1			T1	202		T2	15		T4	179
auto[0]	auto[1]	interest[64]	3920	1			T1	97		T2	5		T4	88
auto[1]	auto[0]	others[0]	12817	1			T5	39		T7	109		T9	13
auto[1]	auto[0]	others[1]	2090	1			T5	8		T7	18		T9	4
auto[1]	auto[0]	others[2]	2121	1			T5	4		T7	22		T9	1
auto[1]	auto[0]	others[3]	2475	1			T5	9		T7	26		T9	2
auto[1]	auto[0]	interest[1]	1372	1			T5	5		T7	10		T9	1
auto[1]	auto[0]	interest[4]	8329	1			T5	27		T7	70		T9	8
auto[1]	auto[0]	interest[64]	4101	1			T5	15		T7	33		T9	4

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal