Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	938	1			T19	18		T24	20		T44	4
all_values[1]	938	1			T19	18		T24	20		T44	4
all_values[2]	938	1			T19	18		T24	20		T44	4
all_values[3]	938	1			T19	18		T24	20		T44	4
all_values[4]	938	1			T19	18		T24	20		T44	4
all_values[5]	938	1			T19	18		T24	20		T44	4
all_values[6]	938	1			T19	18		T24	20		T44	4
all_values[7]	938	1			T19	18		T24	20		T44	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3983

1

T19

77

T24

95

T44

20

auto[1]

3521

1

T19

67

T24

65

T44

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2997

1

T19

54

T24

55

T44

16

auto[1]

4507

1

T19

90

T24

105

T44

16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4265

1

T19

82

T24

90

T44

21

auto[1]

3239

1

T19

62

T24

70

T44

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	216	1			T19	4		T24	3		T44	4
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T19	1		T24	3		T35	2
all_values[0]	auto[0]	auto[1]	auto[0]	166	1			T19	6		T24	3		T35	2
all_values[0]	auto[0]	auto[1]	auto[1]	85	1			T19	2		T24	2		T36	2
all_values[0]	auto[1]	auto[0]	auto[1]	203	1			T19	3		T24	5		T35	2
all_values[0]	auto[1]	auto[1]	auto[1]	181	1			T19	2		T24	4		T35	1
all_values[1]	auto[0]	auto[0]	auto[0]	187	1			T19	5		T24	5		T44	1
all_values[1]	auto[0]	auto[0]	auto[1]	99	1			T19	2		T24	1		T44	1
all_values[1]	auto[0]	auto[1]	auto[0]	164	1			T19	2		T44	1		T35	3
all_values[1]	auto[0]	auto[1]	auto[1]	97	1			T24	2		T35	1		T36	4
all_values[1]	auto[1]	auto[0]	auto[1]	202	1			T19	8		T24	5		T35	1
all_values[1]	auto[1]	auto[1]	auto[1]	189	1			T19	1		T24	7		T44	1
all_values[2]	auto[0]	auto[0]	auto[0]	185	1			T19	2		T24	6		T44	2
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T24	3		T35	2		T36	1
all_values[2]	auto[0]	auto[1]	auto[0]	152	1			T19	4		T24	1		T35	1
all_values[2]	auto[0]	auto[1]	auto[1]	75	1			T19	1		T24	3		T35	1
all_values[2]	auto[1]	auto[0]	auto[1]	227	1			T24	3		T35	3		T36	4
all_values[2]	auto[1]	auto[1]	auto[1]	209	1			T19	11		T24	4		T44	2
all_values[3]	auto[0]	auto[0]	auto[0]	196	1			T19	1		T24	3		T44	1
all_values[3]	auto[0]	auto[0]	auto[1]	91	1			T19	2		T24	3		T44	1
all_values[3]	auto[0]	auto[1]	auto[0]	158	1			T19	2		T24	2		T35	3
all_values[3]	auto[0]	auto[1]	auto[1]	93	1			T19	5		T24	3		T35	1
all_values[3]	auto[1]	auto[0]	auto[1]	193	1			T19	3		T24	5		T44	2
all_values[3]	auto[1]	auto[1]	auto[1]	207	1			T19	5		T24	4		T35	1
all_values[4]	auto[0]	auto[0]	auto[0]	169	1			T19	2		T24	7		T35	1
all_values[4]	auto[0]	auto[0]	auto[1]	117	1			T19	5		T24	3		T35	1
all_values[4]	auto[0]	auto[1]	auto[0]	177	1			T19	4		T24	2		T44	1
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T19	1		T24	1		T35	2
all_values[4]	auto[1]	auto[0]	auto[1]	235	1			T19	3		T24	3		T44	1
all_values[4]	auto[1]	auto[1]	auto[1]	167	1			T19	3		T24	4		T44	2
all_values[5]	auto[0]	auto[0]	auto[0]	273	1			T19	7		T24	8		T44	3
all_values[5]	auto[0]	auto[1]	auto[0]	246	1			T19	4		T24	1		T35	4
all_values[5]	auto[1]	auto[0]	auto[1]	237	1			T19	5		T24	7		T44	1
all_values[5]	auto[1]	auto[1]	auto[1]	182	1			T19	2		T24	4		T35	2
all_values[6]	auto[0]	auto[0]	auto[0]	194	1			T19	5		T24	8		T44	1
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T19	2		T24	3		T44	1
all_values[6]	auto[0]	auto[1]	auto[0]	153	1			T19	1		T24	1		T35	1
all_values[6]	auto[0]	auto[1]	auto[1]	103	1			T19	1		T24	1		T44	1
all_values[6]	auto[1]	auto[0]	auto[1]	211	1			T19	5		T24	3		T35	2
all_values[6]	auto[1]	auto[1]	auto[1]	197	1			T19	4		T24	4		T44	1
all_values[7]	auto[0]	auto[0]	auto[0]	203	1			T19	3		T24	1		T44	1
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T19	3		T24	5		T35	2
all_values[7]	auto[0]	auto[1]	auto[0]	158	1			T19	2		T24	4		T44	1
all_values[7]	auto[0]	auto[1]	auto[1]	93	1			T19	3		T24	2		T44	1
all_values[7]	auto[1]	auto[0]	auto[1]	203	1			T19	6		T24	2		T35	3
all_values[7]	auto[1]	auto[1]	auto[1]	196	1			T19	1		T24	6		T44	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal