Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7557635	1			T1	1		T2	1		T3	38357
all_values[1]	7557635	1			T1	1		T2	1		T3	38357
all_values[2]	7557635	1			T1	1		T2	1		T3	38357
all_values[3]	7557635	1			T1	1		T2	1		T3	38357
all_values[4]	7557635	1			T1	1		T2	1		T3	38357
all_values[5]	7557635	1			T1	1		T2	1		T3	38357
all_values[6]	7557635	1			T1	1		T2	1		T3	38357
all_values[7]	7557635	1			T1	1		T2	1		T3	38357

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58012302

1

T1

8

T2

8

T3

306856

auto[1]

2448778

1

T14

89038

T23

24

T62

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60379577

1

T1

8

T2

8

T3

306008

auto[1]

81503

1

T3

848

T14

1281

T22

154

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7266429	1			T1	1		T2	1		T3	37762
all_values[0]	auto[0]	auto[1]	45120	1			T3	595		T14	740		T22	86
all_values[0]	auto[1]	auto[0]	243606	1			T14	3		T23	2		T62	2
all_values[0]	auto[1]	auto[1]	2480	1			T23	1		T135	2		T153	5
all_values[1]	auto[0]	auto[0]	7389774	1			T1	1		T2	1		T3	38164
all_values[1]	auto[0]	auto[1]	22903	1			T3	193		T14	1		T22	34
all_values[1]	auto[1]	auto[0]	143852	1			T14	17362		T23	3		T62	2
all_values[1]	auto[1]	auto[1]	1106	1			T14	445		T135	1		T153	6
all_values[2]	auto[0]	auto[0]	7421947	1			T1	1		T2	1		T3	38297
all_values[2]	auto[0]	auto[1]	7380	1			T3	60		T14	1		T22	34
all_values[2]	auto[1]	auto[0]	127686	1			T14	17725		T23	1		T62	7
all_values[2]	auto[1]	auto[1]	622	1			T14	81		T23	1		T153	6
all_values[3]	auto[0]	auto[0]	7414516	1			T1	1		T2	1		T3	38357
all_values[3]	auto[0]	auto[1]	174	1			T23	3		T62	1		T159	1
all_values[3]	auto[1]	auto[0]	142777	1			T14	17803		T23	1		T62	1
all_values[3]	auto[1]	auto[1]	168	1			T14	2		T23	1		T62	1
all_values[4]	auto[0]	auto[0]	6988992	1			T1	1		T2	1		T3	38357
all_values[4]	auto[0]	auto[1]	188	1			T14	1		T23	1		T62	3
all_values[4]	auto[1]	auto[0]	568297	1			T14	17804		T23	6		T62	1
all_values[4]	auto[1]	auto[1]	158	1			T14	1		T135	1		T153	4
all_values[5]	auto[0]	auto[0]	7323596	1			T1	1		T2	1		T3	38357
all_values[5]	auto[0]	auto[1]	340	1			T14	2		T23	2		T160	1
all_values[5]	auto[1]	auto[0]	233542	1			T14	1		T23	1		T62	2
all_values[5]	auto[1]	auto[1]	157	1			T14	2		T23	2		T62	1
all_values[6]	auto[0]	auto[0]	7048428	1			T1	1		T2	1		T3	38357
all_values[6]	auto[0]	auto[1]	173	1			T14	1		T62	3		T135	3
all_values[6]	auto[1]	auto[0]	508846	1			T14	2		T23	1		T62	2
all_values[6]	auto[1]	auto[1]	188	1			T23	1		T135	1		T153	3
all_values[7]	auto[0]	auto[0]	7082165	1			T1	1		T2	1		T3	38357
all_values[7]	auto[0]	auto[1]	177	1			T14	1		T23	3		T62	3
all_values[7]	auto[1]	auto[0]	475124	1			T14	17804		T23	1		T62	1
all_values[7]	auto[1]	auto[1]	169	1			T14	3		T23	2		T62	3