Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	39469	1			T3	178		T5	18		T10	4
auto[SpiFlashAddrCfg]	9379	1			T3	43		T10	2		T12	4
auto[SpiFlashAddr3b]	11239	1			T3	45		T9	4		T12	4
auto[SpiFlashAddr4b]	9163	1			T3	41		T9	2		T12	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40475

1

T3

184

T5

18

T9

6

auto[1]

28775

1

T3

123

T12

10

T11

22

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37308

1

T3

171

T5

18

T12

6

auto[1]

31942

1

T3

136

T9

6

T10

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	45089	1			T3	199		T5	18		T9	2
values[1]	1359	1			T3	9		T14	9		T15	2
values[2]	1775	1			T3	13		T9	2		T10	2
values[3]	1811	1			T3	11		T14	9		T15	2
values[4]	1755	1			T3	4		T11	2		T14	3
values[5]	1840	1			T3	9		T14	8		T22	3
values[6]	1725	1			T3	5		T12	2		T13	8
values[7]	1765	1			T3	7		T12	2		T13	2
values[8]	12131	1			T3	50		T9	2		T10	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36846

1

T5

18

T9

6

T10

6

auto[1]

32404

1

T3

307

T14

416

T22

153

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

66606

1

T3

292

T5

18

T9

6

write

2644

1

T3

15

T12

2

T14

29

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

24188

1

T3

139

T5

18

T9

4

valids[0x1]

45062

1

T3

168

T9

2

T10

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1974	1			T3	11		T14	9		T15	2
internal_process_ops[0x5a]	1920	1			T3	7		T9	2		T12	2
internal_process_ops[0x05]	22625	1			T3	58		T10	2		T14	144
internal_process_ops[0x35]	1906	1			T3	10		T14	18		T15	2
internal_process_ops[0x15]	1988	1			T3	14		T14	17		T15	3
internal_process_ops[0x03]	1356	1			T3	1		T10	2		T14	4
internal_process_ops[0x0b]	1326	1			T3	2		T12	2		T11	2
internal_process_ops[0x3b]	1382	1			T3	3		T11	4		T13	6
internal_process_ops[0x6b]	1408	1			T3	1		T14	2		T28	4
internal_process_ops[0xbb]	1368	1			T3	2		T9	2		T12	2
internal_process_ops[0xeb]	1352	1			T3	3		T11	2		T14	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67954

1

T3

303

T5

18

T9

6

auto[1]

1296

1

T3

4

T12

2

T14

23

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66783

1

T3

282

T5

18

T9

6

auto[1]

2467

1

T3

25

T14

30

T22

5

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12718

1

T5

18

T10

4

T15

13

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6793

1

T15

6

T23

95

T24

149

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2678

1

T10

2

T13

10

T15

7

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2380

1

T12

4

T11

12

T15

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3271

1

T9

4

T13

4

T15

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2759

1

T12

2

T11

10

T15

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2692

1

T9

2

T13

12

T15

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2238

1

T12

2

T15

3

T23

29

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

120

1

T23

2

T24

4

T26

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

66

1

T23

1

T24

3

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T23

1

T31

3

T33

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

73

1

T26

2

T31

1

T33

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

82

1

T23

5

T31

2

T155

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

55

1

T24

2

T26

1

T33

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

64

1

T26

2

T42

2

T31

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

119

1

T29

2

T31

2

T32

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

108

1

T31

1

T32

2

T33

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

62

1

T23

1

T24

1

T35

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

60

1

T23

3

T33

2

T34

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

92

1

T12

2

T29

4

T30

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T28

8

T23

5

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

77

1

T23

1

T24

3

T32

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

75

1

T23

4

T26

1

T31

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

83

1

T23

1

T24

1

T31

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11506

1

T3

114

T14

177

T22

67

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7798

1

T3

60

T14

73

T22

17

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2003

1

T3

19

T14

25

T22

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1650

1

T3

18

T14

16

T22

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2419

1

T3

17

T14

30

T22

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2165

1

T3

23

T14

31

T22

13

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1857

1

T3

22

T14

17

T22

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1679

1

T3

19

T14

18

T22

14

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

85

1

T3

3

T22

2

T23

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

75

1

T3

1

T156

1

T157

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

68

1

T25

1

T41

1

T37

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

82

1

T14

4

T22

1

T23

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

99

1

T3

5

T14

1

T23

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

86

1

T14

2

T22

1

T25

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

87

1

T3

1

T14

3

T23

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

76

1

T14

6

T120

2

T37

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

72

1

T3

2

T14

1

T25

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

69

1

T3

1

T14

4

T23

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

74

1

T25

4

T82

1

T37

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

88

1

T3

2

T14

4

T25

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

87

1

T14

1

T82

2

T37

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

92

1

T14

2

T23

1

T25

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

86

1

T22

1

T25

1

T82

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T14

1

T22

1

T25

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	5110	1			T5	18		T11	2		T13	6
auto[0]	values[0]	valids[0x1]	17769	1			T9	2		T10	2		T12	4
auto[0]	values[1]	valids[0x1]	691	1			T15	2		T23	8		T24	7
auto[0]	values[2]	valids[0x0]	662	1			T9	2		T23	10		T24	6
auto[0]	values[2]	valids[0x1]	330	1			T10	2		T13	2		T23	6
auto[0]	values[3]	valids[0x0]	661	1			T15	2		T23	6		T24	3
auto[0]	values[3]	valids[0x1]	433	1			T23	6		T24	4		T158	4
auto[0]	values[4]	valids[0x0]	643	1			T23	12		T24	4		T158	4
auto[0]	values[4]	valids[0x1]	352	1			T11	2		T23	7		T24	1
auto[0]	values[5]	valids[0x0]	712	1			T23	13		T24	16		T29	2
auto[0]	values[5]	valids[0x1]	392	1			T23	7		T24	9		T26	8
auto[0]	values[6]	valids[0x0]	673	1			T12	2		T13	6		T15	3
auto[0]	values[6]	valids[0x1]	354	1			T13	2		T23	4		T24	7
auto[0]	values[7]	valids[0x0]	678	1			T13	2		T23	12		T24	6
auto[0]	values[7]	valids[0x1]	355	1			T12	2		T23	3		T24	3
auto[0]	values[8]	valids[0x0]	4415	1			T9	2		T11	14		T13	4
auto[0]	values[8]	valids[0x1]	2616	1			T10	2		T12	2		T11	2
auto[1]	values[0]	valids[0x0]	4813	1			T3	77		T14	63		T22	30
auto[1]	values[0]	valids[0x1]	17397	1			T3	122		T14	240		T22	70
auto[1]	values[1]	valids[0x1]	668	1			T3	9		T14	9		T22	3
auto[1]	values[2]	valids[0x0]	486	1			T3	9		T14	5		T22	4
auto[1]	values[2]	valids[0x1]	297	1			T3	4		T14	2		T22	2
auto[1]	values[3]	valids[0x0]	443	1			T3	5		T14	5		T22	1
auto[1]	values[3]	valids[0x1]	274	1			T3	6		T14	4		T23	4
auto[1]	values[4]	valids[0x0]	446	1			T3	1		T14	2		T22	3
auto[1]	values[4]	valids[0x1]	314	1			T3	3		T14	1		T23	4
auto[1]	values[5]	valids[0x0]	487	1			T3	7		T14	1		T22	3
auto[1]	values[5]	valids[0x1]	249	1			T3	2		T14	7		T23	4
auto[1]	values[6]	valids[0x0]	421	1			T3	4		T14	4		T22	4
auto[1]	values[6]	valids[0x1]	277	1			T3	1		T14	2		T22	3
auto[1]	values[7]	valids[0x0]	449	1			T3	5		T14	8		T22	2
auto[1]	values[7]	valids[0x1]	283	1			T3	2		T14	2		T22	3
auto[1]	values[8]	valids[0x0]	3089	1			T3	31		T14	40		T22	20
auto[1]	values[8]	valids[0x1]	2011	1			T3	19		T14	21		T22	5