Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19569

1

T3

107

T5

20

T9

1

auto[1]

22911

1

T3

72

T14

166

T22

38

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16381

1

T3

97

T5

20

T9

1

auto[1]

26099

1

T3

82

T10

2

T14

179

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	6471	1			T3	22		T5	3		T9	1
auto[524288:1048575]	5058	1			T3	44		T22	6		T36	2
auto[1048576:1572863]	5227	1			T3	22		T5	7		T14	27
auto[1572864:2097151]	5384	1			T3	25		T14	61		T15	2
auto[2097152:2621439]	5360	1			T3	10		T5	2		T14	26
auto[2621440:3145727]	4857	1			T3	14		T5	6		T14	38
auto[3145728:3670015]	4849	1			T3	23		T5	2		T14	33
auto[3670016:4194303]	5274	1			T3	19		T14	49		T15	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41580

1

T3

178

T5

20

T9

1

auto[1]

900

1

T3

1

T22

3

T23

7

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34302

1

T3

130

T5

7

T9

1

auto[1]

8178

1

T3

49

T5

13

T14

19

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1970	1			T3	4		T5	3		T9	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	788	1			T3	2		T10	2		T14	5
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1369	1			T3	14		T22	3		T36	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	545	1			T3	7		T22	3		T23	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1320	1			T3	2		T14	6		T15	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	542	1			T3	3		T14	5		T15	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1375	1			T3	5		T14	19		T15	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	565	1			T3	4		T14	8		T15	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1283	1			T3	3		T5	2		T14	8
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	550	1			T3	2		T14	4		T22	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1302	1			T3	5		T5	2		T14	8
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	491	1			T3	4		T14	6		T15	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1358	1			T3	8		T14	7		T15	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	539	1			T3	4		T14	3		T23	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1381	1			T3	9		T14	14		T15	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	479	1			T3	2		T14	6		T22	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	330	1			T3	6		T14	2		T15	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	170	1			T3	4		T14	1		T15	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	286	1			T3	3		T23	2		T24	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	152	1			T3	1		T23	2		T25	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	356	1			T3	6		T5	7		T23	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	136	1			T23	2		T24	1		T25	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	313	1			T3	4		T14	2		T22	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	145	1			T3	2		T14	2		T22	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	351	1			T22	1		T23	10		T25	7
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	156	1			T23	4		T25	4		T31	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	280	1			T3	2		T5	4		T90	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	135	1			T23	2		T82	1		T32	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	303	1			T5	2		T23	5		T24	7
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	124	1			T23	1		T24	5		T43	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	336	1			T3	1		T14	2		T22	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	139	1			T14	3		T23	2		T25	3
auto[1]	auto[0]	auto[0:524287]	auto[0]	304	1			T14	7		T22	1		T23	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2451	1			T14	28		T22	3		T23	8
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	263	1			T3	6		T26	2		T27	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1924	1			T3	10		T26	6		T27	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	253	1			T3	1		T14	4		T23	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2005	1			T3	1		T14	12		T23	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	263	1			T3	2		T14	5		T23	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2238	1			T3	6		T14	18		T23	37
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	225	1			T3	2		T14	3		T22	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2085	1			T3	3		T14	11		T22	26
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	228	1			T3	1		T14	3		T22	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1846	1			T3	2		T14	21		T22	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	232	1			T3	4		T14	3		T23	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1807	1			T3	7		T14	20		T23	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	233	1			T3	2		T14	4		T23	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2088	1			T3	5		T14	20		T23	47
auto[1]	auto[1]	auto[0:524287]	auto[0]	64	1			T3	2		T32	1		T33	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	394	1			T3	4		T32	12		T33	14
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	57	1			T3	1		T24	1		T25	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	462	1			T3	2		T24	8		T25	69
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	74	1			T3	3		T43	2		T35	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	541	1			T3	6		T43	10		T35	19
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	55	1			T3	1		T14	1		T23	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	430	1			T3	1		T14	6		T23	13
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	65	1			T23	1		T25	1		T32	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	645	1			T23	16		T25	28		T32	15
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	48	1			T33	2		T35	3		T37	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	527	1			T33	48		T35	20		T37	28
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	51	1			T23	2		T24	1		T43	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	435	1			T23	12		T24	1		T43	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	53	1			T23	1		T26	1		T37	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	565	1			T23	48		T26	16		T37	11

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	15485	1			T3	78		T5	7		T9	1
auto[0]	auto[0]	auto[1]	372	1			T22	1		T23	3		T24	11
auto[0]	auto[1]	auto[0]	3631	1			T3	29		T5	13		T14	12
auto[0]	auto[1]	auto[1]	81	1			T23	1		T25	2		T43	1
auto[1]	auto[0]	auto[0]	18082	1			T3	51		T14	159		T22	36
auto[1]	auto[0]	auto[1]	363	1			T3	1		T22	2		T23	3
auto[1]	auto[1]	auto[0]	4382	1			T3	20		T14	7		T23	96
auto[1]	auto[1]	auto[1]	84	1			T24	1		T43	4		T32	2