Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22025

1

T5

18

T9

6

T10

6

auto[1]

14821

1

T12

10

T11

22

T15

14

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3979	1			T9	6		T28	26		T23	84
values[1]	4707	1			T12	10		T23	131		T24	90
values[2]	4457	1			T13	26		T23	42		T24	20
values[3]	4462	1			T10	6		T15	20		T23	20
values[4]	4487	1			T15	20		T23	77		T24	62
values[5]	5474	1			T5	18		T23	189		T24	88
values[6]	4449	1			T23	20		T24	114		T27	34
values[7]	4831	1			T11	22		T205	16		T26	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4207	1			T28	26		T23	123		T24	30
values[1]	4325	1			T9	6		T23	20		T24	94
values[2]	5047	1			T23	40		T24	48		T84	10
values[3]	4789	1			T12	10		T15	20		T23	56
values[4]	4059	1			T5	18		T23	85		T24	111
values[5]	4795	1			T11	22		T15	20		T23	155
values[6]	4537	1			T23	44		T24	40		T29	38
values[7]	5087	1			T10	6		T13	26		T23	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	301	1			T28	26		T26	12		T71	2
auto[0]	values[0]	values[1]	150	1			T9	6		T206	34		T47	14
auto[0]	values[0]	values[2]	504	1			T23	11		T31	22		T32	8
auto[0]	values[0]	values[3]	191	1			T83	8		T31	9		T207	20
auto[0]	values[0]	values[4]	265	1			T23	14		T196	22		T79	15
auto[0]	values[0]	values[5]	324	1			T26	10		T34	13		T155	17
auto[0]	values[0]	values[6]	423	1			T23	10		T73	20		T19	30
auto[0]	values[0]	values[7]	279	1			T23	15		T26	12		T91	12
auto[0]	values[1]	values[0]	280	1			T23	54		T33	30		T79	4
auto[0]	values[1]	values[1]	390	1			T31	10		T32	21		T196	11
auto[0]	values[1]	values[2]	356	1			T32	21		T35	29		T78	95
auto[0]	values[1]	values[3]	406	1			T24	31		T33	33		T35	53
auto[0]	values[1]	values[4]	423	1			T24	32		T32	28		T78	9
auto[0]	values[1]	values[5]	260	1			T23	13		T90	22		T35	8
auto[0]	values[1]	values[6]	146	1			T152	11		T199	5		T45	12
auto[0]	values[1]	values[7]	389	1			T23	13		T208	16		T152	70
auto[0]	values[2]	values[0]	274	1			T23	14		T26	27		T33	14
auto[0]	values[2]	values[1]	204	1			T168	18		T209	2		T190	13
auto[0]	values[2]	values[2]	421	1			T34	10		T35	49		T136	12
auto[0]	values[2]	values[3]	248	1			T23	14		T210	10		T45	11
auto[0]	values[2]	values[4]	303	1			T31	32		T35	16		T155	7
auto[0]	values[2]	values[5]	337	1			T26	12		T70	18		T31	12
auto[0]	values[2]	values[6]	457	1			T24	9		T31	21		T33	10
auto[0]	values[2]	values[7]	476	1			T13	26		T42	9		T32	14
auto[0]	values[3]	values[0]	407	1			T23	12		T34	6		T78	11
auto[0]	values[3]	values[1]	341	1			T19	13		T154	10		T211	4
auto[0]	values[3]	values[2]	370	1			T24	22		T33	13		T78	17
auto[0]	values[3]	values[3]	315	1			T179	52		T136	14		T199	12
auto[0]	values[3]	values[4]	224	1			T24	8		T35	9		T152	11
auto[0]	values[3]	values[5]	323	1			T15	12		T24	10		T79	10
auto[0]	values[3]	values[6]	281	1			T33	17		T35	14		T136	7
auto[0]	values[3]	values[7]	380	1			T10	6		T155	37		T19	17
auto[0]	values[4]	values[0]	461	1			T42	12		T32	18		T34	10
auto[0]	values[4]	values[1]	445	1			T24	11		T33	11		T179	92
auto[0]	values[4]	values[2]	251	1			T34	14		T155	8		T194	32
auto[0]	values[4]	values[3]	363	1			T15	14		T33	9		T78	9
auto[0]	values[4]	values[4]	274	1			T23	11		T24	6		T35	41
auto[0]	values[4]	values[5]	309	1			T23	12		T31	10		T32	12
auto[0]	values[4]	values[6]	220	1			T23	7		T33	13		T212	4
auto[0]	values[4]	values[7]	295	1			T78	12		T19	15		T154	13
auto[0]	values[5]	values[0]	301	1			T23	8		T24	9		T69	18
auto[0]	values[5]	values[1]	421	1			T23	10		T26	22		T31	11
auto[0]	values[5]	values[2]	332	1			T23	7		T32	8		T213	16
auto[0]	values[5]	values[3]	418	1			T23	28		T24	29		T35	27
auto[0]	values[5]	values[4]	341	1			T5	18		T23	15		T32	21
auto[0]	values[5]	values[5]	451	1			T23	61		T19	20		T136	14
auto[0]	values[5]	values[6]	461	1			T32	45		T33	10		T178	36
auto[0]	values[5]	values[7]	465	1			T24	14		T31	9		T33	25
auto[0]	values[6]	values[0]	333	1			T31	15		T188	21		T45	15
auto[0]	values[6]	values[1]	280	1			T24	45		T33	13		T152	14
auto[0]	values[6]	values[2]	362	1			T24	14		T32	26		T34	10
auto[0]	values[6]	values[3]	370	1			T32	15		T155	29		T19	11
auto[0]	values[6]	values[4]	416	1			T23	14		T24	11		T34	7
auto[0]	values[6]	values[5]	398	1			T27	26		T214	2		T152	50
auto[0]	values[6]	values[6]	436	1			T24	9		T32	23		T215	14
auto[0]	values[6]	values[7]	232	1			T216	12		T19	14		T152	14
auto[0]	values[7]	values[0]	325	1			T32	12		T35	33		T155	26
auto[0]	values[7]	values[1]	283	1			T205	16		T217	16		T152	18
auto[0]	values[7]	values[2]	646	1			T34	10		T155	15		T179	13
auto[0]	values[7]	values[3]	418	1			T218	26		T179	40		T45	9
auto[0]	values[7]	values[4]	243	1			T26	11		T154	13		T47	10
auto[0]	values[7]	values[5]	357	1			T26	15		T136	7		T219	10
auto[0]	values[7]	values[6]	239	1			T32	25		T35	13		T152	10
auto[0]	values[7]	values[7]	431	1			T40	86		T220	14		T136	32
auto[1]	values[0]	values[0]	155	1			T26	8		T78	8		T136	9
auto[1]	values[0]	values[1]	103	1			T47	6		T221	9		T137	7
auto[1]	values[0]	values[2]	207	1			T23	9		T31	2		T32	13
auto[1]	values[0]	values[3]	122	1			T31	11		T193	8		T221	20
auto[1]	values[0]	values[4]	185	1			T23	6		T196	14		T79	11
auto[1]	values[0]	values[5]	158	1			T26	10		T34	9		T155	3
auto[1]	values[0]	values[6]	381	1			T23	14		T29	38		T19	5
auto[1]	values[0]	values[7]	231	1			T23	5		T26	16		T34	7
auto[1]	values[1]	values[0]	164	1			T23	7		T33	8		T79	50
auto[1]	values[1]	values[1]	295	1			T31	19		T32	9		T196	9
auto[1]	values[1]	values[2]	337	1			T30	28		T32	19		T35	6
auto[1]	values[1]	values[3]	271	1			T12	10		T24	10		T33	3
auto[1]	values[1]	values[4]	274	1			T24	17		T32	4		T78	11
auto[1]	values[1]	values[5]	294	1			T23	37		T35	31		T155	19
auto[1]	values[1]	values[6]	182	1			T152	23		T199	20		T45	8
auto[1]	values[1]	values[7]	240	1			T23	7		T152	14		T136	17
auto[1]	values[2]	values[0]	226	1			T23	8		T158	20		T26	10
auto[1]	values[2]	values[1]	159	1			T190	31		T222	10		T223	14
auto[1]	values[2]	values[2]	222	1			T34	10		T35	6		T136	9
auto[1]	values[2]	values[3]	316	1			T23	6		T224	32		T171	28
auto[1]	values[2]	values[4]	185	1			T31	16		T35	10		T155	13
auto[1]	values[2]	values[5]	175	1			T26	8		T31	10		T34	11
auto[1]	values[2]	values[6]	192	1			T24	11		T31	24		T33	10
auto[1]	values[2]	values[7]	262	1			T42	11		T32	6		T35	7
auto[1]	values[3]	values[0]	225	1			T23	8		T93	16		T34	14
auto[1]	values[3]	values[1]	148	1			T19	16		T154	10		T225	24
auto[1]	values[3]	values[2]	209	1			T24	6		T33	7		T78	9
auto[1]	values[3]	values[3]	188	1			T179	15		T136	23		T199	10
auto[1]	values[3]	values[4]	163	1			T24	12		T35	11		T152	18
auto[1]	values[3]	values[5]	286	1			T15	8		T24	83		T79	10
auto[1]	values[3]	values[6]	220	1			T33	8		T35	20		T136	42
auto[1]	values[3]	values[7]	382	1			T177	14		T155	6		T19	8
auto[1]	values[4]	values[0]	247	1			T42	8		T32	5		T34	11
auto[1]	values[4]	values[1]	322	1			T24	31		T33	9		T179	14
auto[1]	values[4]	values[2]	151	1			T34	6		T155	12		T226	5
auto[1]	values[4]	values[3]	316	1			T15	6		T33	67		T78	11
auto[1]	values[4]	values[4]	215	1			T23	9		T24	14		T35	9
auto[1]	values[4]	values[5]	228	1			T23	25		T31	10		T32	8
auto[1]	values[4]	values[6]	203	1			T23	13		T33	7		T179	17
auto[1]	values[4]	values[7]	187	1			T78	8		T19	19		T154	7
auto[1]	values[5]	values[0]	169	1			T23	12		T24	21		T19	4
auto[1]	values[5]	values[1]	322	1			T23	10		T26	5		T31	9
auto[1]	values[5]	values[2]	205	1			T23	13		T84	10		T32	12
auto[1]	values[5]	values[3]	451	1			T23	8		T24	9		T35	20
auto[1]	values[5]	values[4]	142	1			T23	10		T32	19		T152	5
auto[1]	values[5]	values[5]	246	1			T23	7		T19	4		T136	8
auto[1]	values[5]	values[6]	297	1			T92	20		T32	4		T33	22
auto[1]	values[5]	values[7]	452	1			T24	6		T31	11		T33	89
auto[1]	values[6]	values[0]	178	1			T31	7		T188	11		T45	6
auto[1]	values[6]	values[1]	170	1			T24	7		T33	41		T152	7
auto[1]	values[6]	values[2]	251	1			T24	6		T32	9		T34	10
auto[1]	values[6]	values[3]	173	1			T32	5		T155	7		T19	9
auto[1]	values[6]	values[4]	219	1			T23	6		T24	11		T34	13
auto[1]	values[6]	values[5]	196	1			T27	8		T152	11		T154	16
auto[1]	values[6]	values[6]	270	1			T24	11		T32	9		T78	5
auto[1]	values[6]	values[7]	165	1			T19	8		T152	6		T199	10
auto[1]	values[7]	values[0]	161	1			T32	8		T35	13		T155	5
auto[1]	values[7]	values[1]	292	1			T152	2		T79	7		T45	13
auto[1]	values[7]	values[2]	223	1			T34	18		T155	8		T179	7
auto[1]	values[7]	values[3]	223	1			T179	9		T45	11		T46	20
auto[1]	values[7]	values[4]	187	1			T26	9		T154	7		T47	29
auto[1]	values[7]	values[5]	453	1			T11	22		T26	5		T227	18
auto[1]	values[7]	values[6]	129	1			T32	15		T35	7		T152	13
auto[1]	values[7]	values[7]	221	1			T136	8		T154	8		T182	7