Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	499	1			T23	2		T24	3		T26	3
auto[ReadAddrCrossIntoMailbox]	365	1			T23	5		T24	4		T26	1
auto[ReadAddrCrossOutOfMailbox]	375	1			T24	6		T26	4		T31	3
auto[ReadAddrCrossAllMailbox]	272	1			T23	2		T24	4		T26	2
auto[ReadAddrOutsideMailbox]	4521	1			T9	2		T10	2		T12	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3019

1

T9

1

T10

1

T12

2

auto[1]

3013

1

T9

1

T10

1

T12

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	988	1			T10	2		T15	1		T23	17
read_ops[0x0b]	990	1			T12	2		T11	2		T13	4
read_ops[0x3b]	1023	1			T11	4		T13	6		T23	10
read_ops[0x6b]	1037	1			T28	4		T23	21		T24	6
read_ops[0xbb]	987	1			T9	2		T12	2		T15	1
read_ops[0xeb]	1007	1			T11	2		T15	1		T23	15

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T33	1		T196	1		T147	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T23	1		T26	1		T32	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T155	1		T179	1		T152	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T32	1		T35	1		T136	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T26	2		T19	2		T152	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T26	1		T31	1		T35	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T31	1		T32	1		T33	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T23	2		T155	2		T78	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T10	1		T23	3		T24	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	422	1			T10	1		T15	1		T23	11
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T26	1		T33	2		T35	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T23	1		T24	1		T26	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T32	1		T179	2		T136	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T32	2		T179	1		T152	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T24	2		T155	2		T78	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T24	2		T31	1		T32	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T24	1		T154	2		T45	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T24	1		T26	1		T35	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	404	1			T12	1		T11	1		T13	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	345	1			T12	1		T11	1		T13	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T32	1		T155	1		T78	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	53	1			T33	1		T155	2		T179	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T24	1		T155	1		T136	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T23	1		T24	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T33	1		T78	1		T179	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T35	1		T196	2		T19	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T24	1		T33	1		T35	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	29	1			T32	1		T196	2		T201	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	369	1			T11	2		T13	3		T23	5
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	391	1			T11	2		T13	3		T23	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T91	2		T32	2		T35	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T91	2		T196	1		T152	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T35	1		T78	1		T179	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T23	2		T155	1		T179	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T19	1		T152	1		T154	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T32	1		T33	2		T35	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T35	1		T136	1		T154	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T78	1		T187	1		T47	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	393	1			T28	2		T23	13		T24	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	394	1			T28	2		T23	6		T24	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T24	1		T91	3		T147	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T91	3		T31	1		T32	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	39	1			T24	1		T32	1		T33	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T23	2		T24	1		T32	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T24	1		T33	1		T152	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T24	1		T26	1		T32	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T19	1		T152	1		T79	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T24	1		T26	1		T34	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	387	1			T9	1		T12	1		T23	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	366	1			T9	1		T12	1		T15	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	50	1			T33	1		T35	1		T78	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	50	1			T24	1		T32	1		T155	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T31	1		T32	1		T35	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T26	1		T194	1		T179	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T32	1		T33	1		T78	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T31	1		T35	1		T78	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	30	1			T33	1		T155	1		T78	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T32	1		T194	1		T179	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	365	1			T11	1		T15	1		T23	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	358	1			T11	1		T23	11		T24	5