Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7557635	1			T1	1		T2	1		T3	38357
all_pins[1]	7557635	1			T1	1		T2	1		T3	38357
all_pins[2]	7557635	1			T1	1		T2	1		T3	38357
all_pins[3]	7557635	1			T1	1		T2	1		T3	38357
all_pins[4]	7557635	1			T1	1		T2	1		T3	38357
all_pins[5]	7557635	1			T1	1		T2	1		T3	38357
all_pins[6]	7557635	1			T1	1		T2	1		T3	38357
all_pins[7]	7557635	1			T1	1		T2	1		T3	38357

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	59942205	1			T1	8		T2	8		T3	306856
values[0x1]	518875	1			T14	556		T23	8		T62	5
transitions[0x0=>0x1]	515381	1			T14	472		T23	5		T62	5
transitions[0x1=>0x0]	515389	1			T14	472		T23	5		T62	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7555039	1			T1	1		T2	1		T3	38357
all_pins[0]	values[0x1]	2596	1			T23	1		T135	2		T153	5
all_pins[0]	transitions[0x0=>0x1]	2323	1			T23	1		T135	2		T153	5
all_pins[0]	transitions[0x1=>0x0]	881	1			T14	464		T135	1		T153	6
all_pins[1]	values[0x0]	7556481	1			T1	1		T2	1		T3	38357
all_pins[1]	values[0x1]	1154	1			T14	464		T135	1		T153	6
all_pins[1]	transitions[0x0=>0x1]	979	1			T14	382		T135	1		T153	3
all_pins[1]	transitions[0x1=>0x0]	472	1			T14	2		T23	1		T153	3
all_pins[2]	values[0x0]	7556988	1			T1	1		T2	1		T3	38357
all_pins[2]	values[0x1]	647	1			T14	84		T23	1		T153	6
all_pins[2]	transitions[0x0=>0x1]	597	1			T14	82		T153	6		T136	4
all_pins[2]	transitions[0x1=>0x0]	118	1			T62	1		T135	2		T153	1
all_pins[3]	values[0x0]	7557467	1			T1	1		T2	1		T3	38357
all_pins[3]	values[0x1]	168	1			T14	2		T23	1		T62	1
all_pins[3]	transitions[0x0=>0x1]	129	1			T14	2		T23	1		T62	1
all_pins[3]	transitions[0x1=>0x0]	119	1			T14	1		T135	1		T153	4
all_pins[4]	values[0x0]	7557477	1			T1	1		T2	1		T3	38357
all_pins[4]	values[0x1]	158	1			T14	1		T135	1		T153	4
all_pins[4]	transitions[0x0=>0x1]	126	1			T14	1		T135	1		T153	3
all_pins[4]	transitions[0x1=>0x0]	5698	1			T14	2		T23	2		T62	1
all_pins[5]	values[0x0]	7551905	1			T1	1		T2	1		T3	38357
all_pins[5]	values[0x1]	5730	1			T14	2		T23	2		T62	1
all_pins[5]	transitions[0x0=>0x1]	2892	1			T14	2		T23	2		T62	1
all_pins[5]	transitions[0x1=>0x0]	505415	1			T23	1		T135	1		T153	3
all_pins[6]	values[0x0]	7049382	1			T1	1		T2	1		T3	38357
all_pins[6]	values[0x1]	508253	1			T23	1		T135	1		T153	3
all_pins[6]	transitions[0x0=>0x1]	508204	1			T153	3		T136	4		T154	144881
all_pins[6]	transitions[0x1=>0x0]	120	1			T14	3		T23	1		T62	3
all_pins[7]	values[0x0]	7557466	1			T1	1		T2	1		T3	38357
all_pins[7]	values[0x1]	169	1			T14	3		T23	2		T62	3
all_pins[7]	transitions[0x0=>0x1]	131	1			T14	3		T23	1		T62	3
all_pins[7]	transitions[0x1=>0x0]	2566	1			T135	1		T153	2		T136	1