Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5045	1			T23	146		T24	113		T205	16
values[1]	4853	1			T10	6		T11	22		T15	20
values[2]	4090	1			T5	18		T12	10		T23	106
values[3]	4722	1			T13	26		T23	102		T24	148
values[4]	4301	1			T23	20		T29	38		T26	57
values[5]	4800	1			T28	26		T24	114		T26	20
values[6]	4804	1			T23	81		T24	40		T90	22
values[7]	4231	1			T9	6		T15	20		T23	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5159	1			T9	6		T11	22		T23	76
values[1]	3976	1			T23	20		T24	20		T29	38
values[2]	4062	1			T15	20		T24	93		T84	10
values[3]	4870	1			T10	6		T15	20		T23	112
values[4]	4247	1			T23	20		T24	89		T83	8
values[5]	5210	1			T13	26		T23	97		T24	70
values[6]	4377	1			T12	10		T23	92		T24	42
values[7]	4945	1			T5	18		T28	26		T23	146

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36219

1

T5

18

T9

6

T10

6

auto[1]

627

1

T12

2

T23

4

T24

10

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	515	1			T23	55		T205	16		T227	18
auto[0]	values[0]	values[1]	681	1			T26	18		T177	14		T31	22
auto[0]	values[0]	values[2]	632	1			T24	93		T136	19		T228	6
auto[0]	values[0]	values[3]	471	1			T196	36		T19	29		T154	20
auto[0]	values[0]	values[4]	722	1			T24	20		T32	35		T33	51
auto[0]	values[0]	values[5]	813	1			T23	20		T73	20		T42	20
auto[0]	values[0]	values[6]	459	1			T23	50		T196	22		T136	20
auto[0]	values[0]	values[7]	664	1			T23	20		T34	40		T179	35
auto[0]	values[1]	values[0]	782	1			T11	22		T31	22		T33	20
auto[0]	values[1]	values[1]	443	1			T136	20		T199	20		T219	20
auto[0]	values[1]	values[2]	386	1			T84	10		T33	38		T202	24
auto[0]	values[1]	values[3]	704	1			T10	6		T15	20		T23	68
auto[0]	values[1]	values[4]	579	1			T35	53		T214	2		T136	26
auto[0]	values[1]	values[5]	840	1			T23	20		T33	20		T35	20
auto[0]	values[1]	values[6]	482	1			T31	22		T152	18		T136	20
auto[0]	values[1]	values[7]	569	1			T155	22		T210	10		T136	19
auto[0]	values[2]	values[0]	368	1			T24	42		T34	22		T154	27
auto[0]	values[2]	values[1]	433	1			T32	47		T136	20		T199	44
auto[0]	values[2]	values[2]	538	1			T78	20		T179	18		T199	20
auto[0]	values[2]	values[3]	579	1			T31	21		T35	33		T78	20
auto[0]	values[2]	values[4]	574	1			T79	40		T197	52		T229	18
auto[0]	values[2]	values[5]	595	1			T23	20		T158	20		T179	30
auto[0]	values[2]	values[6]	534	1			T12	8		T24	20		T27	34
auto[0]	values[2]	values[7]	407	1			T5	18		T23	85		T155	29
auto[0]	values[3]	values[0]	435	1			T23	20		T35	45		T224	32
auto[0]	values[3]	values[1]	468	1			T23	20		T71	2		T34	18
auto[0]	values[3]	values[2]	373	1			T136	20		T197	20		T230	2
auto[0]	values[3]	values[3]	659	1			T23	20		T24	29		T91	12
auto[0]	values[3]	values[4]	452	1			T24	68		T83	8		T152	20
auto[0]	values[3]	values[5]	748	1			T13	26		T24	25		T26	20
auto[0]	values[3]	values[6]	668	1			T23	22		T40	86		T34	18
auto[0]	values[3]	values[7]	828	1			T23	20		T24	20		T32	20
auto[0]	values[4]	values[0]	571	1			T26	20		T34	20		T196	69
auto[0]	values[4]	values[1]	453	1			T29	32		T70	18		T194	32
auto[0]	values[4]	values[2]	491	1			T32	31		T33	20		T154	20
auto[0]	values[4]	values[3]	628	1			T26	37		T31	27		T32	20
auto[0]	values[4]	values[4]	386	1			T32	20		T19	24		T152	20
auto[0]	values[4]	values[5]	672	1			T32	20		T155	43		T231	10
auto[0]	values[4]	values[6]	593	1			T33	25		T179	20		T19	24
auto[0]	values[4]	values[7]	412	1			T23	20		T32	41		T152	29
auto[0]	values[5]	values[0]	614	1			T136	25		T188	20		T46	20
auto[0]	values[5]	values[1]	527	1			T24	20		T32	20		T78	47
auto[0]	values[5]	values[2]	673	1			T199	20		T45	101		T232	21
auto[0]	values[5]	values[3]	462	1			T26	20		T19	34		T171	22
auto[0]	values[5]	values[4]	502	1			T78	26		T181	38		T233	8
auto[0]	values[5]	values[5]	661	1			T24	20		T30	26		T31	25
auto[0]	values[5]	values[6]	738	1			T24	21		T33	20		T78	46
auto[0]	values[5]	values[7]	558	1			T28	26		T24	49		T33	32
auto[0]	values[6]	values[0]	959	1			T179	66		T136	22		T79	54
auto[0]	values[6]	values[1]	533	1			T31	20		T78	20		T152	20
auto[0]	values[6]	values[2]	464	1			T42	20		T34	21		T35	20
auto[0]	values[6]	values[3]	716	1			T23	24		T32	52		T196	20
auto[0]	values[6]	values[4]	586	1			T32	20		T45	43		T221	24
auto[0]	values[6]	values[5]	454	1			T23	36		T24	20		T32	41
auto[0]	values[6]	values[6]	420	1			T23	19		T90	22		T93	16
auto[0]	values[6]	values[7]	603	1			T24	20		T31	24		T32	20
auto[0]	values[7]	values[0]	850	1			T9	6		T24	38		T31	21
auto[0]	values[7]	values[1]	341	1			T26	74		T216	12		T78	20
auto[0]	values[7]	values[2]	438	1			T15	20		T45	28		T182	20
auto[0]	values[7]	values[3]	556	1			T208	16		T33	68		T152	22
auto[0]	values[7]	values[4]	383	1			T23	20		T79	20		T199	58
auto[0]	values[7]	values[5]	334	1			T234	18		T45	20		T48	20
auto[0]	values[7]	values[6]	426	1			T235	16		T190	20		T184	19
auto[0]	values[7]	values[7]	814	1			T32	30		T33	20		T35	56
auto[1]	values[0]	values[0]	10	1			T23	1		T47	2		T48	2
auto[1]	values[0]	values[1]	10	1			T26	2		T31	1		T46	1
auto[1]	values[0]	values[2]	8	1			T136	1		T226	1		T236	1
auto[1]	values[0]	values[3]	10	1			T187	3		T49	1		T237	1
auto[1]	values[0]	values[4]	13	1			T33	3		T152	2		T223	2
auto[1]	values[0]	values[5]	17	1			T179	3		T182	2		T238	6
auto[1]	values[0]	values[6]	4	1			T239	3		T240	1		-	-
auto[1]	values[0]	values[7]	16	1			T19	1		T47	1		T241	3
auto[1]	values[1]	values[0]	6	1			T34	1		T179	1		T137	2
auto[1]	values[1]	values[1]	6	1			T45	1		T242	1		T243	4
auto[1]	values[1]	values[2]	12	1			T244	8		T182	1		T245	2
auto[1]	values[1]	values[3]	5	1			T19	1		T246	1		T169	2
auto[1]	values[1]	values[4]	10	1			T35	2		T154	1		T222	1
auto[1]	values[1]	values[5]	16	1			T179	2		T19	2		T49	1
auto[1]	values[1]	values[6]	3	1			T152	2		T169	1		-	-
auto[1]	values[1]	values[7]	10	1			T136	1		T154	2		T46	3
auto[1]	values[2]	values[0]	4	1			T154	1		T237	2		T247	1
auto[1]	values[2]	values[1]	8	1			T32	2		T199	1		T248	2
auto[1]	values[2]	values[2]	6	1			T179	2		T249	1		T250	1
auto[1]	values[2]	values[3]	12	1			T31	1		T35	2		T49	3
auto[1]	values[2]	values[4]	11	1			T79	1		T197	2		T229	2
auto[1]	values[2]	values[5]	12	1			T179	3		T152	1		T45	1
auto[1]	values[2]	values[6]	4	1			T12	2		T155	1		T47	1
auto[1]	values[2]	values[7]	5	1			T23	1		T155	2		T79	1
auto[1]	values[3]	values[0]	6	1			T35	2		T179	1		T46	2
auto[1]	values[3]	values[1]	9	1			T34	2		T45	1		T46	1
auto[1]	values[3]	values[2]	8	1			T184	1		T251	2		T250	3
auto[1]	values[3]	values[3]	13	1			T31	1		T46	1		T193	2
auto[1]	values[3]	values[4]	7	1			T24	1		T193	1		T137	2
auto[1]	values[3]	values[5]	16	1			T24	5		T34	1		T190	2
auto[1]	values[3]	values[6]	15	1			T34	2		T182	1		T252	2
auto[1]	values[3]	values[7]	17	1			T222	1		T48	1		T252	5
auto[1]	values[4]	values[0]	11	1			T196	1		T223	1		T253	1
auto[1]	values[4]	values[1]	27	1			T29	6		T189	3		T137	1
auto[1]	values[4]	values[2]	8	1			T32	1		T187	1		T49	1
auto[1]	values[4]	values[3]	13	1			T31	2		T33	1		T154	2
auto[1]	values[4]	values[4]	4	1			T19	1		T190	1		T254	2
auto[1]	values[4]	values[5]	14	1			T193	5		T185	1		T248	1
auto[1]	values[4]	values[6]	11	1			T188	2		T190	2		T137	1
auto[1]	values[4]	values[7]	7	1			T152	1		T136	1		T190	1
auto[1]	values[5]	values[0]	5	1			T136	2		T242	1		T237	1
auto[1]	values[5]	values[1]	12	1			T47	3		T221	2		T49	1
auto[1]	values[5]	values[2]	10	1			T45	2		T232	1		T21	3
auto[1]	values[5]	values[3]	13	1			T171	6		T185	1		T222	1
auto[1]	values[5]	values[4]	1	1			T199	1		-	-		-	-
auto[1]	values[5]	values[5]	7	1			T30	2		T35	2		T219	1
auto[1]	values[5]	values[6]	11	1			T24	1		T45	2		T255	4
auto[1]	values[5]	values[7]	6	1			T24	3		T184	1		T49	2
auto[1]	values[6]	values[0]	8	1			T179	1		T256	1		T250	2
auto[1]	values[6]	values[1]	6	1			T48	1		T239	1		T257	1
auto[1]	values[6]	values[2]	5	1			T221	1		T258	1		T259	3
auto[1]	values[6]	values[3]	21	1			T260	1		T190	2		T184	2
auto[1]	values[6]	values[4]	9	1			T221	1		T261	1		T246	1
auto[1]	values[6]	values[5]	8	1			T23	1		T32	2		T184	1
auto[1]	values[6]	values[6]	4	1			T23	1		T222	1		T52	2
auto[1]	values[6]	values[7]	8	1			T154	3		T253	2		T249	1
auto[1]	values[7]	values[0]	15	1			T31	2		T152	3		T199	2
auto[1]	values[7]	values[1]	19	1			T26	1		T225	6		T221	1
auto[1]	values[7]	values[2]	10	1			T185	1		T184	1		T262	2
auto[1]	values[7]	values[3]	8	1			T33	1		T152	1		T260	2
auto[1]	values[7]	values[4]	8	1			T199	2		T263	3		T249	2
auto[1]	values[7]	values[5]	3	1			T264	2		T265	1		-	-
auto[1]	values[7]	values[6]	5	1			T184	1		T261	1		T266	2
auto[1]	values[7]	values[7]	21	1			T35	2		T79	2		T219	1