Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2869

1

T1

8

T2

5

T3

11

auto[1]

2744

1

T1

11

T2

12

T3

14

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3054

1

T3

25

T16

25

T14

39

auto[1]

2559

1

T1

19

T2

17

T4

39

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4429

1

T1

19

T2

17

T3

17

auto[1]

1184

1

T3

8

T16

8

T14

16

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1131	1			T1	5		T2	3		T3	6
valid[1]	1185	1			T1	4		T2	3		T3	4
valid[2]	1138	1			T1	3		T2	5		T3	6
valid[3]	1079	1			T1	3		T2	4		T3	4
valid[4]	1080	1			T1	4		T2	2		T3	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	194	1			T3	2		T16	3		T22	1
auto[0]	auto[0]	valid[0]	auto[1]	255	1			T1	1		T4	6		T16	1
auto[0]	auto[0]	valid[1]	auto[0]	198	1			T3	1		T16	2		T14	3
auto[0]	auto[0]	valid[1]	auto[1]	266	1			T1	2		T2	2		T4	4
auto[0]	auto[0]	valid[2]	auto[0]	187	1			T3	2		T16	2		T14	5
auto[0]	auto[0]	valid[2]	auto[1]	253	1			T1	1		T2	2		T4	2
auto[0]	auto[0]	valid[3]	auto[0]	177	1			T3	1		T16	3		T14	1
auto[0]	auto[0]	valid[3]	auto[1]	269	1			T1	2		T2	1		T4	5
auto[0]	auto[0]	valid[4]	auto[0]	197	1			T3	2		T16	1		T14	1
auto[0]	auto[0]	valid[4]	auto[1]	255	1			T1	2		T4	4		T14	2
auto[0]	auto[1]	valid[0]	auto[0]	166	1			T3	2		T16	1		T14	3
auto[0]	auto[1]	valid[0]	auto[1]	276	1			T1	4		T2	3		T4	3
auto[0]	auto[1]	valid[1]	auto[0]	199	1			T3	1		T16	1		T14	4
auto[0]	auto[1]	valid[1]	auto[1]	264	1			T1	2		T2	1		T4	1
auto[0]	auto[1]	valid[2]	auto[0]	204	1			T3	2		T16	3		T14	1
auto[0]	auto[1]	valid[2]	auto[1]	229	1			T1	2		T2	3		T4	2
auto[0]	auto[1]	valid[3]	auto[0]	184	1			T3	1		T16	1		T14	2
auto[0]	auto[1]	valid[3]	auto[1]	247	1			T1	1		T2	3		T4	3
auto[0]	auto[1]	valid[4]	auto[0]	164	1			T3	3		T14	3		T15	3
auto[0]	auto[1]	valid[4]	auto[1]	245	1			T1	2		T2	2		T4	9
auto[1]	auto[0]	valid[0]	auto[0]	127	1			T3	2		T14	3		T26	1
auto[1]	auto[0]	valid[1]	auto[0]	137	1			T16	2		T14	1		T23	1
auto[1]	auto[0]	valid[2]	auto[0]	132	1			T16	1		T14	3		T15	1
auto[1]	auto[0]	valid[3]	auto[0]	101	1			T3	1		T14	1		T22	1
auto[1]	auto[0]	valid[4]	auto[0]	121	1			T16	1		T14	3		T26	1
auto[1]	auto[1]	valid[0]	auto[0]	113	1			T16	1		T14	2		T15	1
auto[1]	auto[1]	valid[1]	auto[0]	121	1			T3	2		T23	1		T27	1
auto[1]	auto[1]	valid[2]	auto[0]	133	1			T3	2		T16	1		T26	1
auto[1]	auto[1]	valid[3]	auto[0]	101	1			T3	1		T14	2		T15	1
auto[1]	auto[1]	valid[4]	auto[0]	98	1			T16	2		T14	1		T23	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal