Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76012

1

T3

660

T16

562

T14

1024

auto[1]

27269

1

T1

19

T2

270

T4

484

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75339

1

T1

19

T2

270

T3

430

auto[1]

27942

1

T3

230

T16

213

T14

384

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	53140	1			T1	19		T2	142		T3	339
others[1]	8725	1			T2	14		T3	55		T4	51
others[2]	8678	1			T2	29		T3	56		T4	43
others[3]	9856	1			T2	25		T3	61		T4	42
interest[1]	5610	1			T2	17		T3	31		T4	15
interest[4]	34642	1			T1	19		T2	93		T3	212
interest[64]	17272	1			T2	43		T3	118		T4	86

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	24654	1			T3	222		T16	170		T14	341
auto[0]	auto[0]	others[1]	4080	1			T3	36		T16	29		T14	48
auto[0]	auto[0]	others[2]	4045	1			T3	37		T16	24		T14	61
auto[0]	auto[0]	others[3]	4554	1			T3	36		T16	35		T14	54
auto[0]	auto[0]	interest[1]	2665	1			T3	20		T16	24		T14	46
auto[0]	auto[0]	interest[4]	16083	1			T3	143		T16	108		T14	230
auto[0]	auto[0]	interest[64]	8072	1			T3	79		T16	67		T14	90
auto[0]	auto[1]	others[0]	14202	1			T1	19		T2	142		T4	247
auto[0]	auto[1]	others[1]	2259	1			T2	14		T4	51		T16	2
auto[0]	auto[1]	others[2]	2259	1			T2	29		T4	43		T16	10
auto[0]	auto[1]	others[3]	2595	1			T2	25		T4	42		T16	5
auto[0]	auto[1]	interest[1]	1434	1			T2	17		T4	15		T14	5
auto[0]	auto[1]	interest[4]	9351	1			T1	19		T2	93		T4	165
auto[0]	auto[1]	interest[64]	4520	1			T2	43		T4	86		T16	17
auto[1]	auto[0]	others[0]	14284	1			T3	117		T16	116		T14	186
auto[1]	auto[0]	others[1]	2386	1			T3	19		T16	11		T14	39
auto[1]	auto[0]	others[2]	2374	1			T3	19		T16	16		T14	42
auto[1]	auto[0]	others[3]	2707	1			T3	25		T16	22		T14	31
auto[1]	auto[0]	interest[1]	1511	1			T3	11		T16	10		T14	25
auto[1]	auto[0]	interest[4]	9208	1			T3	69		T16	76		T14	125
auto[1]	auto[0]	interest[64]	4680	1			T3	39		T16	38		T14	61

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal