Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	733	1			T14	7		T23	7		T62	7
all_values[1]	733	1			T14	7		T23	7		T62	7
all_values[2]	733	1			T14	7		T23	7		T62	7
all_values[3]	733	1			T14	7		T23	7		T62	7
all_values[4]	733	1			T14	7		T23	7		T62	7
all_values[5]	733	1			T14	7		T23	7		T62	7
all_values[6]	733	1			T14	7		T23	7		T62	7
all_values[7]	733	1			T14	7		T23	7		T62	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3156

1

T14

28

T23

38

T62

31

auto[1]

2708

1

T14

28

T23

18

T62

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2361

1

T14

22

T23

25

T62

23

auto[1]

3503

1

T14

34

T23

31

T62

33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3375

1

T14

30

T23

33

T62

33

auto[1]

2489

1

T14

26

T23

23

T62

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	180	1			T14	4		T23	2		T62	1
all_values[0]	auto[0]	auto[0]	auto[1]	81	1			T14	1		T62	1		T135	2
all_values[0]	auto[0]	auto[1]	auto[0]	130	1			T14	1		T62	2		T153	3
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T23	1		T135	1		T153	3
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T23	2		T62	2		T135	3
all_values[0]	auto[1]	auto[1]	auto[1]	118	1			T14	1		T23	2		T62	1
all_values[1]	auto[0]	auto[0]	auto[0]	135	1			T23	4		T62	2		T135	1
all_values[1]	auto[0]	auto[0]	auto[1]	67	1			T14	1		T62	1		T135	2
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T14	1		T62	2		T135	2
all_values[1]	auto[0]	auto[1]	auto[1]	82	1			T14	1		T135	1		T153	2
all_values[1]	auto[1]	auto[0]	auto[1]	176	1			T14	1		T23	2		T62	1
all_values[1]	auto[1]	auto[1]	auto[1]	140	1			T14	3		T23	1		T62	1
all_values[2]	auto[0]	auto[0]	auto[0]	136	1			T23	3		T135	1		T153	4
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T62	1		T153	4		T45	2
all_values[2]	auto[0]	auto[1]	auto[0]	129	1			T62	5		T135	6		T153	1
all_values[2]	auto[0]	auto[1]	auto[1]	75	1			T14	1		T153	2		T136	2
all_values[2]	auto[1]	auto[0]	auto[1]	169	1			T14	2		T23	4		T135	3
all_values[2]	auto[1]	auto[1]	auto[1]	149	1			T14	4		T62	1		T153	4
all_values[3]	auto[0]	auto[0]	auto[0]	148	1			T14	1		T23	2		T62	3
all_values[3]	auto[0]	auto[0]	auto[1]	66	1			T23	3		T153	1		T136	3
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T14	3		T135	6		T153	2
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T14	1		T62	1		T135	1
all_values[3]	auto[1]	auto[0]	auto[1]	176	1			T14	2		T23	2		T62	3
all_values[3]	auto[1]	auto[1]	auto[1]	134	1			T135	2		T153	4		T136	4
all_values[4]	auto[0]	auto[0]	auto[0]	139	1			T14	1		T23	1		T62	1
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T14	1		T62	2		T135	3
all_values[4]	auto[0]	auto[1]	auto[0]	145	1			T14	1		T23	4		T135	3
all_values[4]	auto[0]	auto[1]	auto[1]	65	1			T153	1		T136	2		T154	2
all_values[4]	auto[1]	auto[0]	auto[1]	160	1			T14	3		T62	3		T135	2
all_values[4]	auto[1]	auto[1]	auto[1]	140	1			T14	1		T23	2		T62	1
all_values[5]	auto[0]	auto[0]	auto[0]	226	1			T14	2		T23	2		T62	2
all_values[5]	auto[0]	auto[1]	auto[0]	184	1			T14	1		T23	1		T62	3
all_values[5]	auto[1]	auto[0]	auto[1]	173	1			T14	2		T23	3		T135	3
all_values[5]	auto[1]	auto[1]	auto[1]	150	1			T14	2		T23	1		T62	2
all_values[6]	auto[0]	auto[0]	auto[0]	168	1			T14	3		T23	3		T62	1
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T62	1		T135	1		T153	3
all_values[6]	auto[0]	auto[1]	auto[0]	110	1			T14	2		T23	2		T62	1
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T153	1		T136	1		T45	3
all_values[6]	auto[1]	auto[0]	auto[1]	161	1			T14	2		T23	1		T62	3
all_values[6]	auto[1]	auto[1]	auto[1]	156	1			T23	1		T62	1		T135	2
all_values[7]	auto[0]	auto[0]	auto[0]	143	1			T14	1		T23	1		T135	2
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T23	2		T62	2		T153	1
all_values[7]	auto[0]	auto[1]	auto[0]	119	1			T14	1		T135	1		T153	1
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T14	2		T23	2		T62	1
all_values[7]	auto[1]	auto[0]	auto[1]	169	1			T14	1		T23	1		T62	1
all_values[7]	auto[1]	auto[1]	auto[1]	146	1			T14	2		T23	1		T62	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal