Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7109026	1			T1	1		T2	9080		T3	1
all_values[1]	7109026	1			T1	1		T2	9080		T3	1
all_values[2]	7109026	1			T1	1		T2	9080		T3	1
all_values[3]	7109026	1			T1	1		T2	9080		T3	1
all_values[4]	7109026	1			T1	1		T2	9080		T3	1
all_values[5]	7109026	1			T1	1		T2	9080		T3	1
all_values[6]	7109026	1			T1	1		T2	9080		T3	1
all_values[7]	7109026	1			T1	1		T2	9080		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55928139

1

T1

8

T2

72598

T3

8

auto[1]

944069

1

T2

42

T9

105

T12

54

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56800611

1

T1

8

T2

72230

T3

8

auto[1]

71597

1

T2

410

T6

1309

T9

89

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6860976	1			T1	1		T2	8883		T3	1
all_values[0]	auto[0]	auto[1]	40799	1			T2	193		T6	604		T9	7
all_values[0]	auto[1]	auto[0]	206526	1			T2	2		T9	3		T12	8
all_values[0]	auto[1]	auto[1]	725	1			T2	2		T9	5		T12	1
all_values[1]	auto[0]	auto[0]	6847754	1			T1	1		T2	8884		T3	1
all_values[1]	auto[0]	auto[1]	19793	1			T2	193		T6	461		T9	6
all_values[1]	auto[1]	auto[0]	241049	1			T2	2		T9	10		T12	2
all_values[1]	auto[1]	auto[1]	430	1			T2	1		T9	5		T12	6
all_values[2]	auto[0]	auto[0]	7068713	1			T1	1		T2	9073		T3	1
all_values[2]	auto[0]	auto[1]	7312	1			T2	1		T6	244		T9	6
all_values[2]	auto[1]	auto[0]	32767	1			T2	2		T9	12		T12	1
all_values[2]	auto[1]	auto[1]	234	1			T2	4		T9	4		T12	3
all_values[3]	auto[0]	auto[0]	7074131	1			T1	1		T2	9071		T3	1
all_values[3]	auto[0]	auto[1]	220	1			T9	6		T12	5		T132	4
all_values[3]	auto[1]	auto[0]	34444	1			T2	7		T9	11		T12	3
all_values[3]	auto[1]	auto[1]	231	1			T2	2		T9	7		T12	1
all_values[4]	auto[0]	auto[0]	7065417	1			T1	1		T2	9074		T3	1
all_values[4]	auto[0]	auto[1]	186	1			T9	3		T12	2		T132	5
all_values[4]	auto[1]	auto[0]	43197	1			T2	6		T9	8		T12	4
all_values[4]	auto[1]	auto[1]	226	1			T9	7		T12	3		T132	4
all_values[5]	auto[0]	auto[0]	6865545	1			T1	1		T2	9071		T3	1
all_values[5]	auto[0]	auto[1]	403	1			T2	4		T9	4		T12	3
all_values[5]	auto[1]	auto[0]	242876	1			T2	1		T9	1		T12	2
all_values[5]	auto[1]	auto[1]	202	1			T2	4		T9	7		T12	5
all_values[6]	auto[0]	auto[0]	7043245	1			T1	1		T2	9075		T3	1
all_values[6]	auto[0]	auto[1]	192	1			T2	1		T9	8		T12	1
all_values[6]	auto[1]	auto[0]	65392	1			T2	3		T9	3		T12	2
all_values[6]	auto[1]	auto[1]	197	1			T2	1		T9	7		T12	4
all_values[7]	auto[0]	auto[0]	7033260	1			T1	1		T2	9073		T3	1
all_values[7]	auto[0]	auto[1]	193	1			T2	2		T9	3		T12	4
all_values[7]	auto[1]	auto[0]	75319	1			T2	3		T9	11		T12	3
all_values[7]	auto[1]	auto[1]	254	1			T2	2		T9	4		T12	6