Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	38365	1			T2	50		T3	8		T6	178
auto[SpiFlashAddrCfg]	8610	1			T2	23		T3	2		T4	6
auto[SpiFlashAddr3b]	10468	1			T2	31		T3	8		T4	7
auto[SpiFlashAddr4b]	8505	1			T2	19		T3	14		T4	7

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37779

1

T2

70

T4

20

T5

11

auto[1]

28169

1

T2

53

T3

32

T6

178

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36217

1

T2

80

T3

20

T4

6

auto[1]

29731

1

T2

43

T3

12

T4

14

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	43776	1			T2	60		T3	20		T4	7
values[1]	1250	1			T2	3		T3	2		T6	8
values[2]	1631	1			T2	4		T6	9		T11	2
values[3]	1633	1			T6	8		T8	4		T12	20
values[4]	1556	1			T2	7		T6	12		T12	25
values[5]	1664	1			T2	8		T6	19		T12	4
values[6]	1615	1			T2	4		T3	2		T5	1
values[7]	1616	1			T2	5		T4	4		T6	20
values[8]	11207	1			T2	32		T3	8		T4	9

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32652

1

T2

123

T3

32

T6

412

auto[1]

33296

1

T4

20

T5

11

T8

14

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

63580

1

T2

115

T3

32

T4

20

write

2368

1

T2

8

T6

23

T12

27

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

22397

1

T2

54

T3

6

T4

6

valids[0x1]

43551

1

T2

69

T3

26

T4

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1869	1			T2	6		T6	13		T12	11
internal_process_ops[0x5a]	1823	1			T2	2		T3	6		T6	11
internal_process_ops[0x05]	22631	1			T2	25		T3	2		T6	42
internal_process_ops[0x35]	1748	1			T2	4		T3	6		T6	17
internal_process_ops[0x15]	1784	1			T2	1		T6	13		T12	17
internal_process_ops[0x03]	1251	1			T2	6		T3	4		T4	7
internal_process_ops[0x0b]	1233	1			T2	4		T3	4		T4	7
internal_process_ops[0x3b]	1213	1			T2	4		T3	2		T4	4
internal_process_ops[0x6b]	1201	1			T2	4		T3	2		T6	17
internal_process_ops[0xbb]	1213	1			T2	1		T6	11		T12	17
internal_process_ops[0xeb]	1222	1			T2	2		T3	2		T4	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64821

1

T2

118

T3

32

T4

20

auto[1]

1127

1

T2

5

T6

11

T12

19

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63667

1

T2

119

T3

32

T4

20

auto[1]

2281

1

T2

4

T6

20

T12

35

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11395

1

T2

29

T6

118

T10

24

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6217

1

T2

20

T3

8

T6

50

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2365

1

T2

11

T6

36

T11

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1935

1

T2

10

T3

2

T6

41

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2889

1

T2

21

T6

37

T11

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2467

1

T2

10

T3

8

T6

35

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2279

1

T2

6

T6

34

T11

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1987

1

T2

8

T3

14

T6

38

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

86

1

T2

1

T6

5

T12

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

63

1

T12

8

T133

1

T114

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

57

1

T6

2

T13

2

T115

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

54

1

T6

3

T12

1

T27

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

70

1

T12

2

T23

2

T26

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

65

1

T6

2

T14

1

T23

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

65

1

T2

2

T6

1

T14

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

72

1

T6

3

T12

2

T134

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T6

1

T12

2

T77

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

76

1

T6

1

T23

1

T26

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

68

1

T6

3

T23

2

T26

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

63

1

T6

1

T12

3

T14

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

81

1

T12

1

T26

5

T28

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

67

1

T2

2

T12

1

T23

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

71

1

T27

1

T115

4

T135

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

72

1

T2

3

T6

1

T12

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11546

1

T33

79

T18

90

T34

330

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8639

1

T33

45

T18

31

T34

96

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1877

1

T4

6

T5

10

T8

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1813

1

T33

14

T18

19

T34

40

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2334

1

T4

7

T33

29

T18

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2199

1

T33

20

T18

23

T34

32

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1899

1

T4

7

T5

1

T8

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1739

1

T33

18

T18

23

T34

20

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

72

1

T34

5

T136

2

T114

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

68

1

T33

1

T18

2

T34

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

88

1

T33

2

T18

3

T34

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

80

1

T34

5

T68

2

T112

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

90

1

T34

6

T68

5

T112

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

81

1

T18

1

T34

3

T68

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

94

1

T18

4

T112

2

T31

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

83

1

T18

1

T34

1

T112

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

67

1

T18

2

T68

1

T114

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

71

1

T34

4

T137

2

T112

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

79

1

T33

2

T18

4

T34

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

67

1

T33

1

T68

4

T112

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

90

1

T34

1

T112

1

T136

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

60

1

T18

2

T34

3

T112

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

75

1

T33

3

T34

2

T113

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

85

1

T33

1

T112

1

T32

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4460	1			T2	11		T6	84		T10	24
auto[0]	values[0]	valids[0x1]	16134	1			T2	49		T3	20		T6	138
auto[0]	values[1]	valids[0x1]	673	1			T2	3		T3	2		T6	8
auto[0]	values[2]	valids[0x0]	647	1			T2	2		T6	6		T12	12
auto[0]	values[2]	valids[0x1]	277	1			T2	2		T6	3		T11	2
auto[0]	values[3]	valids[0x0]	539	1			T6	6		T12	13		T14	1
auto[0]	values[3]	valids[0x1]	342	1			T6	2		T12	7		T13	1
auto[0]	values[4]	valids[0x0]	506	1			T2	4		T6	4		T12	12
auto[0]	values[4]	valids[0x1]	322	1			T2	3		T6	8		T12	13
auto[0]	values[5]	valids[0x0]	572	1			T2	5		T6	16		T12	4
auto[0]	values[5]	valids[0x1]	343	1			T2	3		T6	3		T13	2
auto[0]	values[6]	valids[0x0]	540	1			T2	1		T3	2		T6	20
auto[0]	values[6]	valids[0x1]	323	1			T2	3		T6	6		T12	6
auto[0]	values[7]	valids[0x0]	575	1			T2	5		T6	12		T12	12
auto[0]	values[7]	valids[0x1]	313	1			T6	8		T12	7		T13	2
auto[0]	values[8]	valids[0x0]	3832	1			T2	26		T3	4		T6	63
auto[0]	values[8]	valids[0x1]	2254	1			T2	6		T3	4		T6	25
auto[1]	values[0]	valids[0x0]	5009	1			T33	56		T18	51		T34	92
auto[1]	values[0]	valids[0x1]	18173	1			T4	7		T33	103		T18	106
auto[1]	values[1]	valids[0x1]	577	1			T33	6		T18	6		T34	12
auto[1]	values[2]	valids[0x0]	437	1			T33	7		T18	7		T34	9
auto[1]	values[2]	valids[0x1]	270	1			T33	4		T18	2		T34	2
auto[1]	values[3]	valids[0x0]	443	1			T33	6		T18	12		T34	4
auto[1]	values[3]	valids[0x1]	309	1			T8	4		T33	4		T18	3
auto[1]	values[4]	valids[0x0]	457	1			T33	3		T18	3		T34	7
auto[1]	values[4]	valids[0x1]	271	1			T33	2		T18	6		T34	8
auto[1]	values[5]	valids[0x0]	448	1			T33	10		T18	5		T34	2
auto[1]	values[5]	valids[0x1]	301	1			T33	3		T18	3		T34	8
auto[1]	values[6]	valids[0x0]	463	1			T5	1		T33	5		T18	6
auto[1]	values[6]	valids[0x1]	289	1			T33	4		T34	5		T137	5
auto[1]	values[7]	valids[0x0]	458	1			T4	4		T8	3		T33	2
auto[1]	values[7]	valids[0x1]	270	1			T33	1		T18	1		T34	3
auto[1]	values[8]	valids[0x0]	3011	1			T4	2		T5	10		T33	22
auto[1]	values[8]	valids[0x1]	2110	1			T4	7		T8	7		T33	12