Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18294

1

T2

38

T3

1

T4

12

auto[1]

22931

1

T2

27

T6

51

T12

588

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15356

1

T2

35

T3

1

T4

12

auto[1]

25869

1

T2

30

T6

72

T12

599

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	6777	1			T2	24		T3	1		T4	1
auto[524288:1048575]	4771	1			T2	2		T6	15		T10	1
auto[1048576:1572863]	4926	1			T2	2		T4	4		T5	1
auto[1572864:2097151]	4879	1			T2	7		T4	1		T6	19
auto[2097152:2621439]	5088	1			T2	6		T4	2		T5	1
auto[2621440:3145727]	5153	1			T2	18		T5	7		T6	6
auto[3145728:3670015]	4870	1			T2	4		T4	2		T5	2
auto[3670016:4194303]	4761	1			T2	2		T4	2		T6	44

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40375

1

T2

65

T3

1

T4

12

auto[1]

850

1

T6

1

T12

15

T14

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33522

1

T2

45

T3

1

T4

12

auto[1]

7703

1

T2

20

T6

31

T10

9

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1842	1			T2	9		T3	1		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	766	1			T2	4		T6	4		T12	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1274	1			T2	1		T6	5		T10	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	468	1			T2	1		T6	2		T12	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1245	1			T2	1		T4	4		T5	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	466	1			T6	14		T12	2		T98	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1249	1			T2	1		T4	1		T6	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	532	1			T2	1		T6	4		T12	6
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1205	1			T2	2		T4	2		T5	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	483	1			T6	1		T12	1		T14	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1289	1			T2	4		T5	7		T6	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	432	1			T6	1		T12	5		T13	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1266	1			T2	1		T4	2		T5	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	483	1			T6	8		T12	7		T14	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1270	1			T2	2		T4	2		T6	15
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	461	1			T6	1		T12	8		T13	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	306	1			T12	3		T33	2		T18	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	162	1			T6	1		T33	1		T18	6
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	297	1			T6	1		T12	2		T26	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	129	1			T12	3		T26	2		T33	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	337	1			T2	1		T6	4		T12	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	152	1			T6	1		T12	1		T33	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	277	1			T2	5		T6	4		T10	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	138	1			T6	2		T12	1		T14	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	319	1			T6	1		T12	2		T26	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	140	1			T12	1		T26	3		T27	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	295	1			T2	2		T12	9		T23	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	141	1			T12	2		T34	4		T68	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	313	1			T2	2		T6	3		T10	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	134	1			T2	1		T6	1		T12	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	290	1			T6	5		T12	2		T13	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	133	1			T6	1		T13	1		T14	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	314	1			T2	1		T6	1		T26	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2859	1			T2	10		T6	1		T26	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	216	1			T6	3		T12	4		T14	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1997	1			T6	4		T12	29		T14	9
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	209	1			T6	8		T12	6		T23	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1682	1			T6	9		T12	85		T23	30
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	201	1			T12	1		T18	1		T27	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1955	1			T12	56		T18	7		T27	55
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	221	1			T2	1		T14	1		T26	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2116	1			T2	3		T14	1		T26	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	236	1			T2	1		T12	7		T23	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2350	1			T2	2		T12	142		T23	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	210	1			T12	2		T23	2		T26	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1947	1			T12	3		T23	15		T26	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	227	1			T6	6		T12	4		T14	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2051	1			T6	12		T12	88		T14	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	65	1			T28	1		T114	3		T192	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	463	1			T28	5		T114	4		T192	39
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	54	1			T33	1		T34	1		T68	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	336	1			T33	1		T34	15		T68	7
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	76	1			T6	1		T12	2		T68	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	759	1			T6	2		T12	35		T68	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	50	1			T14	1		T33	2		T34	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	477	1			T14	1		T33	9		T34	18
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	53	1			T12	1		T34	3		T31	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	551	1			T12	18		T34	16		T31	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	42	1			T2	1		T12	3		T34	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	368	1			T2	8		T12	25		T34	7
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	61	1			T12	4		T14	1		T34	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	456	1			T12	62		T14	3		T34	21
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	47	1			T6	1		T12	1		T68	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	282	1			T6	3		T12	10		T68	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	14378	1			T2	27		T3	1		T4	12
auto[0]	auto[0]	auto[1]	353	1			T12	8		T27	4		T34	10
auto[0]	auto[1]	auto[0]	3469	1			T2	11		T6	24		T10	9
auto[0]	auto[1]	auto[1]	94	1			T12	3		T34	1		T68	3
auto[1]	auto[0]	auto[0]	18469	1			T2	18		T6	43		T12	424
auto[1]	auto[0]	auto[1]	322	1			T6	1		T12	3		T23	1
auto[1]	auto[1]	auto[0]	4059	1			T2	9		T6	7		T12	160
auto[1]	auto[1]	auto[1]	81	1			T12	1		T14	1		T34	7