Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19524

1

T2

70

T6

234

T10

24

auto[1]

13128

1

T2

53

T3

32

T6

178

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3838	1			T3	32		T6	23		T12	91
values[1]	3820	1			T6	72		T12	196		T14	21
values[2]	4090	1			T2	51		T6	20		T12	158
values[3]	4107	1			T6	60		T12	89		T13	20
values[4]	4290	1			T2	30		T6	43		T12	100
values[5]	4295	1			T6	20		T12	76		T13	20
values[6]	3901	1			T2	42		T6	90		T10	24
values[7]	4311	1			T6	84		T11	22		T12	173

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3592	1			T2	20		T6	20		T10	24
values[1]	3595	1			T6	87		T12	176		T13	20
values[2]	4464	1			T2	30		T6	42		T12	25
values[3]	3792	1			T6	20		T12	23		T13	20
values[4]	4825	1			T2	53		T6	42		T12	134
values[5]	4188	1			T2	20		T6	43		T12	229
values[6]	3710	1			T6	48		T11	22		T12	173
values[7]	4486	1			T3	32		T6	110		T12	216

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	162	1			T26	11		T28	6		T192	13
auto[0]	values[0]	values[1]	322	1			T194	16		T195	14		T28	15
auto[0]	values[0]	values[2]	338	1			T26	27		T196	35		T192	59
auto[0]	values[0]	values[3]	518	1			T114	13		T134	39		T191	13
auto[0]	values[0]	values[4]	282	1			T133	13		T197	20		T157	40
auto[0]	values[0]	values[5]	209	1			T12	11		T198	4		T154	13
auto[0]	values[0]	values[6]	362	1			T6	8		T114	9		T193	15
auto[0]	values[0]	values[7]	202	1			T12	11		T176	10		T162	15
auto[0]	values[1]	values[0]	236	1			T23	10		T135	11		T157	14
auto[0]	values[1]	values[1]	282	1			T199	18		T193	24		T200	13
auto[0]	values[1]	values[2]	195	1			T201	51		T135	5		T193	12
auto[0]	values[1]	values[3]	322	1			T114	23		T157	14		T191	16
auto[0]	values[1]	values[4]	387	1			T6	13		T12	14		T14	16
auto[0]	values[1]	values[5]	193	1			T12	13		T28	17		T191	12
auto[0]	values[1]	values[6]	215	1			T12	9		T26	17		T29	14
auto[0]	values[1]	values[7]	482	1			T6	33		T133	22		T115	21
auto[0]	values[2]	values[0]	226	1			T2	12		T28	3		T133	13
auto[0]	values[2]	values[1]	294	1			T6	16		T115	15		T157	20
auto[0]	values[2]	values[2]	299	1			T14	7		T26	10		T99	30
auto[0]	values[2]	values[3]	261	1			T26	6		T27	12		T202	16
auto[0]	values[2]	values[4]	402	1			T2	24		T12	12		T98	4
auto[0]	values[2]	values[5]	313	1			T12	15		T28	7		T114	9
auto[0]	values[2]	values[6]	218	1			T26	13		T28	12		T156	13
auto[0]	values[2]	values[7]	304	1			T12	11		T26	13		T203	20
auto[0]	values[3]	values[0]	200	1			T12	31		T157	21		T176	25
auto[0]	values[3]	values[1]	254	1			T13	10		T14	18		T204	18
auto[0]	values[3]	values[2]	361	1			T133	15		T134	27		T205	6
auto[0]	values[3]	values[3]	221	1			T14	12		T134	77		T176	12
auto[0]	values[3]	values[4]	512	1			T6	14		T26	15		T134	104
auto[0]	values[3]	values[5]	161	1			T133	6		T134	20		T193	11
auto[0]	values[3]	values[6]	254	1			T23	14		T134	15		T160	6
auto[0]	values[3]	values[7]	319	1			T6	18		T12	38		T26	49
auto[0]	values[4]	values[0]	237	1			T6	8		T206	20		T161	7
auto[0]	values[4]	values[1]	318	1			T12	11		T115	19		T157	9
auto[0]	values[4]	values[2]	361	1			T2	10		T14	9		T26	11
auto[0]	values[4]	values[3]	277	1			T176	12		T174	67		T207	8
auto[0]	values[4]	values[4]	256	1			T27	14		T28	15		T114	14
auto[0]	values[4]	values[5]	392	1			T6	13		T28	26		T30	15
auto[0]	values[4]	values[6]	226	1			T12	12		T187	28		T28	11
auto[0]	values[4]	values[7]	417	1			T12	45		T115	15		T192	20
auto[0]	values[5]	values[0]	533	1			T114	5		T208	16		T192	10
auto[0]	values[5]	values[1]	238	1			T12	8		T77	10		T27	11
auto[0]	values[5]	values[2]	563	1			T23	10		T40	8		T150	47
auto[0]	values[5]	values[3]	174	1			T6	9		T12	18		T148	13
auto[0]	values[5]	values[4]	370	1			T13	11		T134	8		T157	13
auto[0]	values[5]	values[5]	251	1			T12	23		T28	15		T179	4
auto[0]	values[5]	values[6]	285	1			T28	11		T20	14		T209	2
auto[0]	values[5]	values[7]	411	1			T27	13		T135	5		T176	15
auto[0]	values[6]	values[0]	352	1			T10	24		T12	12		T28	15
auto[0]	values[6]	values[1]	247	1			T6	26		T165	16		T210	18
auto[0]	values[6]	values[2]	259	1			T12	14		T26	15		T133	9
auto[0]	values[6]	values[3]	245	1			T157	10		T191	13		T19	12
auto[0]	values[6]	values[4]	283	1			T2	14		T12	9		T27	12
auto[0]	values[6]	values[5]	434	1			T2	10		T12	10		T26	13
auto[0]	values[6]	values[6]	203	1			T6	21		T14	27		T211	8
auto[0]	values[6]	values[7]	280	1			T6	14		T29	15		T191	13
auto[0]	values[7]	values[0]	214	1			T212	14		T162	34		T182	11
auto[0]	values[7]	values[1]	282	1			T6	9		T12	56		T213	16
auto[0]	values[7]	values[2]	299	1			T6	22		T26	11		T27	32
auto[0]	values[7]	values[3]	324	1			T13	8		T43	12		T214	16
auto[0]	values[7]	values[4]	445	1			T164	24		T41	26		T28	12
auto[0]	values[7]	values[5]	335	1			T6	10		T26	12		T27	58
auto[0]	values[7]	values[6]	363	1			T11	22		T27	85		T114	14
auto[0]	values[7]	values[7]	344	1			T12	30		T27	9		T135	12
auto[1]	values[0]	values[0]	235	1			T26	9		T28	14		T188	26
auto[1]	values[0]	values[1]	207	1			T28	8		T133	4		T115	23
auto[1]	values[0]	values[2]	107	1			T26	15		T192	5		T172	5
auto[1]	values[0]	values[3]	175	1			T114	7		T134	10		T191	12
auto[1]	values[0]	values[4]	195	1			T133	7		T157	14		T156	17
auto[1]	values[0]	values[5]	133	1			T12	60		T154	7		T215	7
auto[1]	values[0]	values[6]	179	1			T6	15		T114	11		T193	6
auto[1]	values[0]	values[7]	212	1			T3	32		T12	9		T176	15
auto[1]	values[1]	values[0]	142	1			T23	25		T135	24		T157	6
auto[1]	values[1]	values[1]	127	1			T163	18		T193	16		T200	7
auto[1]	values[1]	values[2]	107	1			T135	15		T193	9		T172	4
auto[1]	values[1]	values[3]	134	1			T114	33		T157	8		T191	5
auto[1]	values[1]	values[4]	296	1			T6	9		T12	6		T14	5
auto[1]	values[1]	values[5]	182	1			T12	15		T28	4		T191	9
auto[1]	values[1]	values[6]	274	1			T12	139		T26	7		T29	13
auto[1]	values[1]	values[7]	246	1			T6	17		T216	18		T133	18
auto[1]	values[2]	values[0]	200	1			T2	8		T28	17		T133	9
auto[1]	values[2]	values[1]	180	1			T6	4		T115	5		T157	6
auto[1]	values[2]	values[2]	329	1			T14	14		T26	10		T30	15
auto[1]	values[2]	values[3]	116	1			T26	14		T27	8		T114	7
auto[1]	values[2]	values[4]	243	1			T2	7		T12	74		T28	7
auto[1]	values[2]	values[5]	273	1			T12	5		T28	13		T114	17
auto[1]	values[2]	values[6]	266	1			T26	7		T28	8		T156	10
auto[1]	values[2]	values[7]	166	1			T12	41		T26	7		T28	7
auto[1]	values[3]	values[0]	101	1			T12	6		T157	8		T176	3
auto[1]	values[3]	values[1]	260	1			T13	10		T14	2		T134	14
auto[1]	values[3]	values[2]	355	1			T133	5		T134	33		T176	14
auto[1]	values[3]	values[3]	202	1			T14	21		T134	14		T176	8
auto[1]	values[3]	values[4]	314	1			T6	6		T26	5		T134	6
auto[1]	values[3]	values[5]	142	1			T133	14		T134	6		T193	9
auto[1]	values[3]	values[6]	271	1			T23	48		T134	53		T217	28
auto[1]	values[3]	values[7]	180	1			T6	22		T12	14		T26	18
auto[1]	values[4]	values[0]	188	1			T6	12		T161	84		T218	11
auto[1]	values[4]	values[1]	186	1			T12	10		T219	4		T115	6
auto[1]	values[4]	values[2]	268	1			T2	20		T14	11		T26	13
auto[1]	values[4]	values[3]	356	1			T176	9		T181	15		T183	8
auto[1]	values[4]	values[4]	196	1			T27	6		T28	5		T114	8
auto[1]	values[4]	values[5]	297	1			T6	10		T28	18		T30	5
auto[1]	values[4]	values[6]	109	1			T12	13		T28	10		T60	9
auto[1]	values[4]	values[7]	206	1			T12	9		T115	9		T192	34
auto[1]	values[5]	values[0]	171	1			T114	15		T192	11		T157	12
auto[1]	values[5]	values[1]	147	1			T12	12		T27	9		T135	8
auto[1]	values[5]	values[2]	230	1			T23	10		T115	13		T134	25
auto[1]	values[5]	values[3]	94	1			T6	11		T12	5		T148	7
auto[1]	values[5]	values[4]	225	1			T13	9		T158	30		T134	12
auto[1]	values[5]	values[5]	276	1			T12	10		T28	11		T115	6
auto[1]	values[5]	values[6]	131	1			T28	9		T20	6		T220	6
auto[1]	values[5]	values[7]	196	1			T27	50		T135	15		T176	6
auto[1]	values[6]	values[0]	228	1			T12	8		T28	5		T157	6
auto[1]	values[6]	values[1]	82	1			T6	19		T157	24		T221	8
auto[1]	values[6]	values[2]	115	1			T12	11		T26	5		T133	11
auto[1]	values[6]	values[3]	204	1			T157	48		T191	7		T19	8
auto[1]	values[6]	values[4]	142	1			T2	8		T12	19		T27	10
auto[1]	values[6]	values[5]	345	1			T2	10		T12	67		T170	22
auto[1]	values[6]	values[6]	211	1			T6	4		T14	14		T193	15
auto[1]	values[6]	values[7]	271	1			T6	6		T185	16		T29	7
auto[1]	values[7]	values[0]	167	1			T25	18		T162	11		T182	9
auto[1]	values[7]	values[1]	169	1			T6	13		T12	79		T19	9
auto[1]	values[7]	values[2]	278	1			T6	20		T26	9		T27	105
auto[1]	values[7]	values[3]	169	1			T13	12		T193	16		T157	15
auto[1]	values[7]	values[4]	277	1			T28	10		T29	2		T133	5
auto[1]	values[7]	values[5]	252	1			T6	10		T26	11		T27	14
auto[1]	values[7]	values[6]	143	1			T27	5		T222	4		T114	13
auto[1]	values[7]	values[7]	250	1			T12	8		T27	11		T135	63