Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	466	1			T6	5		T12	7		T13	1
auto[ReadAddrCrossIntoMailbox]	302	1			T2	3		T6	6		T12	6
auto[ReadAddrCrossOutOfMailbox]	335	1			T2	2		T6	8		T12	12
auto[ReadAddrCrossAllMailbox]	192	1			T2	1		T6	3		T12	3
auto[ReadAddrOutsideMailbox]	3915	1			T2	15		T3	14		T6	52

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2600

1

T2

11

T3

7

T6

38

auto[1]

2610

1

T2

10

T3

7

T6

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	894	1			T2	6		T3	4		T6	10
read_ops[0x0b]	887	1			T2	4		T3	4		T6	11
read_ops[0x3b]	861	1			T2	4		T3	2		T6	13
read_ops[0x6b]	875	1			T2	4		T3	2		T6	17
read_ops[0xbb]	836	1			T2	1		T6	11		T12	17
read_ops[0xeb]	857	1			T2	2		T3	2		T6	12

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T12	1		T26	3		T164	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T6	2		T26	1		T164	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T12	2		T26	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T26	1		T29	1		T115	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T6	1		T26	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T2	1		T6	1		T12	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T27	1		T153	2		T160	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T2	1		T12	1		T13	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	337	1			T2	4		T3	2		T6	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T3	2		T6	3		T11	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T12	1		T26	1		T164	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T12	1		T14	1		T164	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T2	1		T6	1		T12	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T12	1		T176	1		T148	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T12	3		T26	1		T28	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T12	1		T27	1		T28	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T26	1		T28	1		T176	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T12	1		T134	1		T35	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	319	1			T2	1		T3	2		T6	6
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	338	1			T2	2		T3	2		T6	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T6	1		T14	1		T164	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T13	1		T26	1		T164	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T6	2		T12	1		T27	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T157	1		T160	2		T223	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T6	2		T12	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T6	1		T12	2		T193	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T179	1		T30	1		T157	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T12	1		T13	1		T26	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	342	1			T2	3		T3	1		T6	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T2	1		T3	1		T6	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T6	1		T12	2		T164	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T164	2		T27	1		T165	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T2	1		T12	1		T14	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T2	1		T6	1		T28	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T6	1		T12	2		T14	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T2	1		T6	1		T12	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T14	1		T27	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T26	1		T191	1		T154	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	330	1			T2	1		T3	1		T6	6
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	351	1			T3	1		T6	7		T12	9
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T6	1		T12	1		T164	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T26	4		T164	2		T133	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T26	2		T27	1		T28	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T6	1		T28	1		T191	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T30	1		T115	2		T172	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T6	1		T26	1		T135	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T27	1		T153	1		T224	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T6	1		T133	1		T156	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T6	4		T12	8		T14	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T2	1		T6	3		T12	8
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T14	1		T26	1		T164	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T12	1		T14	1		T164	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T6	1		T26	1		T133	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T27	1		T135	1		T156	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T14	1		T26	1		T115	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T26	1		T133	1		T173	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T6	2		T114	1		T135	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T26	1		T27	1		T29	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	310	1			T3	1		T6	2		T12	6
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	332	1			T2	2		T3	1		T6	7