Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7109026	1			T1	1		T2	9080		T3	1
all_pins[1]	7109026	1			T1	1		T2	9080		T3	1
all_pins[2]	7109026	1			T1	1		T2	9080		T3	1
all_pins[3]	7109026	1			T1	1		T2	9080		T3	1
all_pins[4]	7109026	1			T1	1		T2	9080		T3	1
all_pins[5]	7109026	1			T1	1		T2	9080		T3	1
all_pins[6]	7109026	1			T1	1		T2	9080		T3	1
all_pins[7]	7109026	1			T1	1		T2	9080		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	56799872	1			T1	8		T2	72624		T3	8
values[0x1]	72336	1			T2	16		T9	46		T12	29
transitions[0x0=>0x1]	70126	1			T2	12		T9	38		T12	21
transitions[0x1=>0x0]	70149	1			T2	12		T9	38		T12	22

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7108278	1			T1	1		T2	9078		T3	1
all_pins[0]	values[0x1]	748	1			T2	2		T9	5		T12	1
all_pins[0]	transitions[0x0=>0x1]	590	1			T2	2		T9	3		T33	2
all_pins[0]	transitions[0x1=>0x0]	284	1			T2	1		T9	3		T12	5
all_pins[1]	values[0x0]	7108584	1			T1	1		T2	9079		T3	1
all_pins[1]	values[0x1]	442	1			T2	1		T9	5		T12	6
all_pins[1]	transitions[0x0=>0x1]	384	1			T2	1		T9	5		T12	5
all_pins[1]	transitions[0x1=>0x0]	177	1			T2	4		T9	4		T12	2
all_pins[2]	values[0x0]	7108791	1			T1	1		T2	9076		T3	1
all_pins[2]	values[0x1]	235	1			T2	4		T9	4		T12	3
all_pins[2]	transitions[0x0=>0x1]	180	1			T2	2		T9	4		T12	3
all_pins[2]	transitions[0x1=>0x0]	176	1			T9	7		T12	1		T132	5
all_pins[3]	values[0x0]	7108795	1			T1	1		T2	9078		T3	1
all_pins[3]	values[0x1]	231	1			T2	2		T9	7		T12	1
all_pins[3]	transitions[0x0=>0x1]	171	1			T2	2		T9	6		T12	1
all_pins[3]	transitions[0x1=>0x0]	166	1			T9	6		T12	3		T132	4
all_pins[4]	values[0x0]	7108800	1			T1	1		T2	9080		T3	1
all_pins[4]	values[0x1]	226	1			T9	7		T12	3		T132	4
all_pins[4]	transitions[0x0=>0x1]	181	1			T9	6		T12	2		T132	3
all_pins[4]	transitions[0x1=>0x0]	5039	1			T2	4		T9	6		T12	4
all_pins[5]	values[0x0]	7103942	1			T1	1		T2	9076		T3	1
all_pins[5]	values[0x1]	5084	1			T2	4		T9	7		T12	5
all_pins[5]	transitions[0x0=>0x1]	3388	1			T2	3		T9	5		T12	3
all_pins[5]	transitions[0x1=>0x0]	63420	1			T9	5		T12	2		T132	6
all_pins[6]	values[0x0]	7043910	1			T1	1		T2	9079		T3	1
all_pins[6]	values[0x1]	65116	1			T2	1		T9	7		T12	4
all_pins[6]	transitions[0x0=>0x1]	65050	1			T2	1		T9	7		T12	2
all_pins[6]	transitions[0x1=>0x0]	188	1			T2	2		T9	4		T12	4
all_pins[7]	values[0x0]	7108772	1			T1	1		T2	9078		T3	1
all_pins[7]	values[0x1]	254	1			T2	2		T9	4		T12	6
all_pins[7]	transitions[0x0=>0x1]	182	1			T2	1		T9	2		T12	5
all_pins[7]	transitions[0x1=>0x0]	699	1			T2	1		T9	3		T12	1