Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5167	1			T2	20		T6	22		T12	297
values[1]	4776	1			T6	40		T12	170		T13	20
values[2]	4005	1			T2	22		T6	45		T12	129
values[3]	3692	1			T6	91		T12	20		T14	21
values[4]	4274	1			T2	20		T3	32		T6	111
values[5]	2855	1			T2	30		T6	23		T14	40
values[6]	3993	1			T6	60		T10	24		T12	57
values[7]	3890	1			T2	31		T6	20		T11	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5061	1			T2	30		T6	40		T12	20
values[1]	4788	1			T2	22		T6	20		T12	182
values[2]	3643	1			T6	68		T12	93		T187	28
values[3]	4686	1			T2	20		T6	82		T11	22
values[4]	3425	1			T2	20		T6	68		T12	220
values[5]	3869	1			T6	20		T12	167		T14	41
values[6]	3500	1			T6	71		T10	24		T12	21
values[7]	3680	1			T2	31		T3	32		T6	43

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32120

1

T2

118

T3

32

T6

401

auto[1]

532

1

T2

5

T6

11

T12

19

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	698	1			T225	66		T29	25		T133	20
auto[0]	values[0]	values[1]	839	1			T28	20		T114	32		T115	20
auto[0]	values[0]	values[2]	614	1			T187	28		T43	12		T28	20
auto[0]	values[0]	values[3]	508	1			T2	18		T6	22		T12	111
auto[0]	values[0]	values[4]	708	1			T12	147		T23	59		T158	30
auto[0]	values[0]	values[5]	656	1			T28	46		T30	44		T226	8
auto[0]	values[0]	values[6]	521	1			T30	24		T115	20		T134	20
auto[0]	values[0]	values[7]	538	1			T12	37		T41	26		T115	25
auto[0]	values[1]	values[0]	749	1			T27	20		T199	18		T134	181
auto[0]	values[1]	values[1]	570	1			T6	20		T219	4		T227	16
auto[0]	values[1]	values[2]	561	1			T211	8		T115	29		T176	20
auto[0]	values[1]	values[3]	786	1			T12	51		T166	6		T134	20
auto[0]	values[1]	values[4]	386	1			T12	20		T27	75		T115	34
auto[0]	values[1]	values[5]	652	1			T12	77		T26	24		T27	109
auto[0]	values[1]	values[6]	433	1			T12	19		T13	20		T28	21
auto[0]	values[1]	values[7]	564	1			T6	20		T216	18		T114	20
auto[0]	values[2]	values[0]	483	1			T14	20		T28	21		T29	23
auto[0]	values[2]	values[1]	565	1			T2	22		T26	23		T28	21
auto[0]	values[2]	values[2]	501	1			T6	25		T12	20		T27	70
auto[0]	values[2]	values[3]	685	1			T6	20		T135	75		T176	21
auto[0]	values[2]	values[4]	227	1			T12	30		T23	19		T27	20
auto[0]	values[2]	values[5]	519	1			T14	20		T26	20		T40	8
auto[0]	values[2]	values[6]	606	1			T228	30		T196	35		T115	20
auto[0]	values[2]	values[7]	346	1			T12	74		T26	19		T133	19
auto[0]	values[3]	values[0]	506	1			T12	20		T28	21		T133	22
auto[0]	values[3]	values[1]	585	1			T14	20		T212	14		T176	26
auto[0]	values[3]	values[2]	219	1			T191	20		T156	20		T60	20
auto[0]	values[3]	values[3]	778	1			T6	20		T27	24		T28	21
auto[0]	values[3]	values[4]	416	1			T6	45		T77	10		T26	20
auto[0]	values[3]	values[5]	328	1			T134	20		T193	20		T157	26
auto[0]	values[3]	values[6]	282	1			T6	23		T114	20		T157	28
auto[0]	values[3]	values[7]	527	1			T170	22		T150	47		T153	24
auto[0]	values[4]	values[0]	835	1			T6	17		T26	20		T134	109
auto[0]	values[4]	values[1]	747	1			T12	111		T115	20		T134	62
auto[0]	values[4]	values[2]	344	1			T6	20		T12	28		T26	20
auto[0]	values[4]	values[3]	520	1			T6	20		T27	20		T195	14
auto[0]	values[4]	values[4]	417	1			T2	18		T6	22		T213	16
auto[0]	values[4]	values[5]	354	1			T12	20		T114	20		T148	20
auto[0]	values[4]	values[6]	559	1			T6	25		T26	20		T30	20
auto[0]	values[4]	values[7]	439	1			T3	32		T229	20		T230	21
auto[0]	values[5]	values[0]	504	1			T2	30		T27	62		T28	23
auto[0]	values[5]	values[1]	224	1			T29	20		T133	20		T191	21
auto[0]	values[5]	values[2]	491	1			T26	27		T164	24		T202	16
auto[0]	values[5]	values[3]	423	1			T29	22		T231	20		T193	25
auto[0]	values[5]	values[4]	253	1			T28	20		T193	21		T182	20
auto[0]	values[5]	values[5]	357	1			T14	20		T26	39		T222	4
auto[0]	values[5]	values[6]	253	1			T191	20		T232	48		T233	8
auto[0]	values[5]	values[7]	310	1			T6	22		T14	20		T26	20
auto[0]	values[6]	values[0]	639	1			T6	20		T98	4		T185	16
auto[0]	values[6]	values[1]	650	1			T26	20		T194	16		T157	25
auto[0]	values[6]	values[2]	397	1			T99	30		T28	19		T29	24
auto[0]	values[6]	values[3]	461	1			T13	20		T114	22		T191	19
auto[0]	values[6]	values[4]	488	1			T12	20		T27	38		T28	17
auto[0]	values[6]	values[5]	398	1			T6	20		T12	36		T114	35
auto[0]	values[6]	values[6]	402	1			T6	20		T10	24		T134	67
auto[0]	values[6]	values[7]	475	1			T176	49		T156	32		T160	20
auto[0]	values[7]	values[0]	558	1			T26	44		T176	20		T234	30
auto[0]	values[7]	values[1]	529	1			T12	70		T26	22		T28	21
auto[0]	values[7]	values[2]	444	1			T6	20		T12	43		T28	25
auto[0]	values[7]	values[3]	463	1			T11	22		T12	52		T13	20
auto[0]	values[7]	values[4]	468	1			T25	16		T26	20		T203	20
auto[0]	values[7]	values[5]	534	1			T12	28		T78	18		T23	34
auto[0]	values[7]	values[6]	402	1			T27	20		T210	18		T114	20
auto[0]	values[7]	values[7]	426	1			T2	30		T14	29		T114	21
auto[1]	values[0]	values[0]	10	1			T29	2		T220	1		T235	2
auto[1]	values[0]	values[1]	11	1			T114	1		T135	1		T176	1
auto[1]	values[0]	values[2]	11	1			T134	2		T169	2		T154	1
auto[1]	values[0]	values[3]	6	1			T2	2		T191	1		T236	1
auto[1]	values[0]	values[4]	13	1			T12	1		T23	3		T153	4
auto[1]	values[0]	values[5]	18	1			T30	2		T19	2		T35	1
auto[1]	values[0]	values[6]	7	1			T148	1		T160	3		T128	2
auto[1]	values[0]	values[7]	9	1			T12	1		T161	1		T221	4
auto[1]	values[1]	values[0]	12	1			T134	3		T237	4		T238	1
auto[1]	values[1]	values[1]	9	1			T221	1		T235	2		T239	1
auto[1]	values[1]	values[2]	14	1			T115	2		T176	1		T181	2
auto[1]	values[1]	values[3]	12	1			T12	1		T157	1		T149	1
auto[1]	values[1]	values[4]	6	1			T134	2		T191	1		T148	2
auto[1]	values[1]	values[5]	10	1			T27	3		T230	2		T218	3
auto[1]	values[1]	values[6]	2	1			T12	2		-	-		-	-
auto[1]	values[1]	values[7]	10	1			T135	3		T153	2		T200	2
auto[1]	values[2]	values[0]	14	1			T28	2		T29	2		T162	1
auto[1]	values[2]	values[1]	7	1			T114	1		T134	1		T135	1
auto[1]	values[2]	values[2]	11	1			T27	2		T157	3		T182	1
auto[1]	values[2]	values[3]	9	1			T156	1		T35	2		T240	1
auto[1]	values[2]	values[4]	5	1			T12	2		T23	1		T35	1
auto[1]	values[2]	values[5]	7	1			T14	1		T192	3		T241	1
auto[1]	values[2]	values[6]	11	1			T156	1		T160	1		T35	3
auto[1]	values[2]	values[7]	9	1			T12	3		T26	1		T133	1
auto[1]	values[3]	values[0]	8	1			T35	1		T239	2		T242	5
auto[1]	values[3]	values[1]	15	1			T14	1		T176	2		T148	2
auto[1]	values[3]	values[2]	1	1			T243	1		-	-		-	-
auto[1]	values[3]	values[3]	11	1			T191	1		T215	2		T235	3
auto[1]	values[3]	values[4]	4	1			T6	1		T191	1		T244	2
auto[1]	values[3]	values[5]	5	1			T235	1		T245	2		T38	2
auto[1]	values[3]	values[6]	5	1			T6	2		T153	1		T243	2
auto[1]	values[3]	values[7]	2	1			T161	1		T246	1		-	-
auto[1]	values[4]	values[0]	15	1			T6	3		T134	1		T163	4
auto[1]	values[4]	values[1]	8	1			T162	1		T247	1		T248	2
auto[1]	values[4]	values[2]	5	1			T6	3		T215	2		-	-
auto[1]	values[4]	values[3]	11	1			T172	1		T181	2		T249	2
auto[1]	values[4]	values[4]	5	1			T2	2		T247	3		-	-
auto[1]	values[4]	values[5]	6	1			T235	1		T250	4		T251	1
auto[1]	values[4]	values[6]	5	1			T6	1		T182	1		T249	1
auto[1]	values[4]	values[7]	4	1			T230	1		T252	1		T242	2
auto[1]	values[5]	values[0]	4	1			T27	1		T249	2		T253	1
auto[1]	values[5]	values[1]	4	1			T29	2		T244	1		T241	1
auto[1]	values[5]	values[2]	13	1			T156	2		T181	1		T60	1
auto[1]	values[5]	values[3]	3	1			T235	1		T250	2		-	-
auto[1]	values[5]	values[4]	4	1			T249	1		T254	3		-	-
auto[1]	values[5]	values[5]	3	1			T26	1		T162	1		T20	1
auto[1]	values[5]	values[6]	4	1			T255	4		-	-		-	-
auto[1]	values[5]	values[7]	5	1			T6	1		T240	1		T239	1
auto[1]	values[6]	values[0]	16	1			T193	2		T162	2		T247	1
auto[1]	values[6]	values[1]	13	1			T162	1		T249	1		T238	3
auto[1]	values[6]	values[2]	9	1			T28	3		T29	2		T115	1
auto[1]	values[6]	values[3]	7	1			T191	1		T182	2		T218	2
auto[1]	values[6]	values[4]	14	1			T28	3		T223	1		T19	2
auto[1]	values[6]	values[5]	10	1			T12	1		T114	1		T193	1
auto[1]	values[6]	values[6]	6	1			T134	2		T182	1		T60	1
auto[1]	values[6]	values[7]	8	1			T176	4		T156	1		T244	3
auto[1]	values[7]	values[0]	10	1			T160	1		T182	2		T154	3
auto[1]	values[7]	values[1]	12	1			T12	1		T134	3		T157	5
auto[1]	values[7]	values[2]	8	1			T12	2		T256	2		T252	4
auto[1]	values[7]	values[3]	3	1			T249	3		-	-		-	-
auto[1]	values[7]	values[4]	11	1			T25	2		T134	1		T162	1
auto[1]	values[7]	values[5]	12	1			T12	5		T23	1		T156	1
auto[1]	values[7]	values[6]	2	1			T162	1		T257	1		-	-
auto[1]	values[7]	values[7]	8	1			T2	1		T14	4		T160	1