Group : spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_prev_wr_en 2 0 2 100.00 100 1 1 2
cp_wr_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 4 0 4 100.00 100 1 1 0


Summary for Variable cp_prev_wr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_prev_wr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2612 1 T2 4 T6 25 T10 8
auto[1] 818 1 T2 1 T6 8 T10 2



Summary for Variable cp_wr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_wr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1701 1 T2 2 T6 19 T10 6
auto[1] 1729 1 T2 3 T6 14 T10 4



Summary for Cross cr_all

Samples crossed: cp_wr_en cp_prev_wr_en
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_wr_encp_prev_wr_enCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1327 1 T2 1 T6 14 T10 6
auto[0] auto[1] 374 1 T2 1 T6 5 T12 3
auto[1] auto[0] 1285 1 T2 3 T6 11 T10 2
auto[1] auto[1] 444 1 T6 3 T10 2 T12 7

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