Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2610

1

T2

6

T6

14

T12

10

auto[1]

2662

1

T2

9

T6

10

T12

14

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2819

1

T2

15

T6

24

T12

21

auto[1]

2453

1

T12

3

T14

5

T15

18

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4184

1

T2

10

T6

17

T12

19

auto[1]

1088

1

T2

5

T6

7

T12

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1057	1			T2	1		T6	3		T12	3
valid[1]	1063	1			T2	3		T6	11		T12	9
valid[2]	1005	1			T2	1		T6	4		T12	6
valid[3]	1097	1			T2	4		T6	2		T12	3
valid[4]	1050	1			T2	6		T6	4		T12	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	178	1			T6	2		T12	2		T21	1
auto[0]	auto[0]	valid[0]	auto[1]	231	1			T15	2		T17	3		T75	3
auto[0]	auto[0]	valid[1]	auto[0]	187	1			T6	4		T12	1		T23	2
auto[0]	auto[0]	valid[1]	auto[1]	243	1			T15	3		T17	2		T33	1
auto[0]	auto[0]	valid[2]	auto[0]	172	1			T6	1		T12	1		T14	1
auto[0]	auto[0]	valid[2]	auto[1]	233	1			T17	2		T18	1		T75	1
auto[0]	auto[0]	valid[3]	auto[0]	164	1			T2	1		T6	1		T12	1
auto[0]	auto[0]	valid[3]	auto[1]	254	1			T15	4		T17	5		T33	3
auto[0]	auto[0]	valid[4]	auto[0]	165	1			T2	2		T6	2		T14	1
auto[0]	auto[0]	valid[4]	auto[1]	226	1			T12	1		T14	1		T15	2
auto[0]	auto[1]	valid[0]	auto[0]	166	1			T6	1		T12	1		T21	3
auto[0]	auto[1]	valid[0]	auto[1]	257	1			T15	1		T17	3		T75	1
auto[0]	auto[1]	valid[1]	auto[0]	175	1			T2	1		T6	3		T12	5
auto[0]	auto[1]	valid[1]	auto[1]	236	1			T12	1		T17	1		T18	3
auto[0]	auto[1]	valid[2]	auto[0]	143	1			T2	1		T6	1		T12	2
auto[0]	auto[1]	valid[2]	auto[1]	271	1			T12	1		T14	4		T15	4
auto[0]	auto[1]	valid[3]	auto[0]	194	1			T2	2		T6	1		T12	1
auto[0]	auto[1]	valid[3]	auto[1]	256	1			T15	2		T17	3		T33	2
auto[0]	auto[1]	valid[4]	auto[0]	187	1			T2	3		T6	1		T12	2
auto[0]	auto[1]	valid[4]	auto[1]	246	1			T17	6		T18	3		T75	2
auto[1]	auto[0]	valid[0]	auto[0]	118	1			T2	1		T13	1		T14	1
auto[1]	auto[0]	valid[1]	auto[0]	117	1			T2	1		T6	2		T12	2
auto[1]	auto[0]	valid[2]	auto[0]	99	1			T6	2		T12	1		T14	2
auto[1]	auto[0]	valid[3]	auto[0]	106	1			T2	1		T12	1		T14	1
auto[1]	auto[0]	valid[4]	auto[0]	117	1			T14	1		T21	2		T26	2
auto[1]	auto[1]	valid[0]	auto[0]	107	1			T33	1		T18	1		T267	1
auto[1]	auto[1]	valid[1]	auto[0]	105	1			T2	1		T6	2		T14	1
auto[1]	auto[1]	valid[2]	auto[0]	87	1			T12	1		T14	1		T23	3
auto[1]	auto[1]	valid[3]	auto[0]	123	1			T13	1		T23	1		T33	1
auto[1]	auto[1]	valid[4]	auto[0]	109	1			T2	1		T6	1		T23	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal