Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71140

1

T2

405

T6

537

T12

528

auto[1]

25515

1

T12

60

T13

4

T14

35

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70846

1

T2

278

T6

366

T12

384

auto[1]

25809

1

T2

127

T6

171

T12

204

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	49738	1			T2	203		T6	280		T12	314
others[1]	8276	1			T2	30		T6	54		T12	50
others[2]	8074	1			T2	46		T6	57		T12	46
others[3]	9308	1			T2	31		T6	47		T12	52
interest[1]	5194	1			T2	24		T6	30		T12	41
interest[4]	32500	1			T2	138		T6	181		T12	208
interest[64]	16065	1			T2	71		T6	69		T12	85

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	23236	1			T2	146		T6	194		T12	166
auto[0]	auto[0]	others[1]	3946	1			T2	21		T6	41		T12	26
auto[0]	auto[0]	others[2]	3724	1			T2	30		T6	40		T12	26
auto[0]	auto[0]	others[3]	4344	1			T2	24		T6	30		T12	29
auto[0]	auto[0]	interest[1]	2479	1			T2	17		T6	24		T12	25
auto[0]	auto[0]	interest[4]	15038	1			T2	95		T6	126		T12	115
auto[0]	auto[0]	interest[64]	7602	1			T2	40		T6	37		T12	52
auto[0]	auto[1]	others[0]	13386	1			T12	29		T13	1		T14	19
auto[0]	auto[1]	others[1]	2134	1			T12	5		T13	2		T14	2
auto[0]	auto[1]	others[2]	2103	1			T12	6		T14	4		T15	23
auto[0]	auto[1]	others[3]	2435	1			T12	7		T14	2		T15	27
auto[0]	auto[1]	interest[1]	1359	1			T12	4		T14	1		T15	14
auto[0]	auto[1]	interest[4]	8844	1			T12	18		T13	1		T14	12
auto[0]	auto[1]	interest[64]	4098	1			T12	9		T13	1		T14	7
auto[1]	auto[0]	others[0]	13116	1			T2	57		T6	86		T12	119
auto[1]	auto[0]	others[1]	2196	1			T2	9		T6	13		T12	19
auto[1]	auto[0]	others[2]	2247	1			T2	16		T6	17		T12	14
auto[1]	auto[0]	others[3]	2529	1			T2	7		T6	17		T12	16
auto[1]	auto[0]	interest[1]	1356	1			T2	7		T6	6		T12	12
auto[1]	auto[0]	interest[4]	8618	1			T2	43		T6	55		T12	75
auto[1]	auto[0]	interest[64]	4365	1			T2	31		T6	32		T12	24

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal