Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	904	1			T2	10		T9	21		T12	14
all_values[1]	904	1			T2	10		T9	21		T12	14
all_values[2]	904	1			T2	10		T9	21		T12	14
all_values[3]	904	1			T2	10		T9	21		T12	14
all_values[4]	904	1			T2	10		T9	21		T12	14
all_values[5]	904	1			T2	10		T9	21		T12	14
all_values[6]	904	1			T2	10		T9	21		T12	14
all_values[7]	904	1			T2	10		T9	21		T12	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3832

1

T2

42

T9

94

T12

71

auto[1]

3400

1

T2

38

T9

74

T12

41

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2911

1

T2

36

T9

58

T12

40

auto[1]

4321

1

T2

44

T9

110

T12

72

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4123

1

T2

46

T9

91

T12

59

auto[1]

3109

1

T2

34

T9

77

T12

53

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	200	1			T2	2		T9	5		T12	7
all_values[0]	auto[0]	auto[0]	auto[1]	93	1			T2	2		T9	3		T29	2
all_values[0]	auto[0]	auto[1]	auto[0]	159	1			T2	2		T9	1		T12	3
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T9	4		T12	1		T132	1
all_values[0]	auto[1]	auto[0]	auto[1]	204	1			T2	2		T9	7		T12	3
all_values[0]	auto[1]	auto[1]	auto[1]	170	1			T2	2		T9	1		T132	1
all_values[1]	auto[0]	auto[0]	auto[0]	169	1			T2	2		T9	3		T12	1
all_values[1]	auto[0]	auto[0]	auto[1]	101	1			T2	1		T9	3		T12	3
all_values[1]	auto[0]	auto[1]	auto[0]	153	1			T2	2		T9	4		T28	6
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T9	2		T12	2		T132	2
all_values[1]	auto[1]	auto[0]	auto[1]	207	1			T2	5		T9	4		T12	6
all_values[1]	auto[1]	auto[1]	auto[1]	184	1			T9	5		T12	2		T132	6
all_values[2]	auto[0]	auto[0]	auto[0]	188	1			T2	1		T9	1		T12	3
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T9	2		T12	2		T132	1
all_values[2]	auto[0]	auto[1]	auto[0]	153	1			T2	1		T9	6		T28	1
all_values[2]	auto[0]	auto[1]	auto[1]	97	1			T2	2		T9	2		T132	1
all_values[2]	auto[1]	auto[0]	auto[1]	228	1			T2	2		T9	9		T12	6
all_values[2]	auto[1]	auto[1]	auto[1]	155	1			T2	4		T9	1		T12	3
all_values[3]	auto[0]	auto[0]	auto[0]	181	1			T2	2		T9	2		T12	4
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T9	1		T12	2		T132	1
all_values[3]	auto[0]	auto[1]	auto[0]	145	1			T2	4		T9	3		T12	2
all_values[3]	auto[0]	auto[1]	auto[1]	83	1			T2	2		T9	3		T132	3
all_values[3]	auto[1]	auto[0]	auto[1]	219	1			T9	6		T12	3		T132	3
all_values[3]	auto[1]	auto[1]	auto[1]	193	1			T2	2		T9	6		T12	3
all_values[4]	auto[0]	auto[0]	auto[0]	201	1			T2	4		T9	3		T12	2
all_values[4]	auto[0]	auto[0]	auto[1]	65	1			T9	1		T12	1		T132	2
all_values[4]	auto[0]	auto[1]	auto[0]	158	1			T2	4		T9	4		T12	4
all_values[4]	auto[0]	auto[1]	auto[1]	95	1			T9	3		T12	2		T132	3
all_values[4]	auto[1]	auto[0]	auto[1]	213	1			T9	5		T12	3		T132	4
all_values[4]	auto[1]	auto[1]	auto[1]	172	1			T2	2		T9	5		T12	2
all_values[5]	auto[0]	auto[0]	auto[0]	259	1			T2	2		T9	9		T12	4
all_values[5]	auto[0]	auto[1]	auto[0]	243	1			T9	1		T12	2		T132	3
all_values[5]	auto[1]	auto[0]	auto[1]	217	1			T2	4		T9	6		T12	3
all_values[5]	auto[1]	auto[1]	auto[1]	185	1			T2	4		T9	5		T12	5
all_values[6]	auto[0]	auto[0]	auto[0]	191	1			T2	4		T9	4		T12	4
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T2	1		T9	3		T12	2
all_values[6]	auto[0]	auto[1]	auto[0]	184	1			T2	2		T9	1		T12	1
all_values[6]	auto[0]	auto[1]	auto[1]	80	1			T2	1		T9	3		T12	2
all_values[6]	auto[1]	auto[0]	auto[1]	191	1			T2	1		T9	4		T12	5
all_values[6]	auto[1]	auto[1]	auto[1]	177	1			T2	1		T9	6		T132	5
all_values[7]	auto[0]	auto[0]	auto[0]	176	1			T2	3		T9	8		T12	3
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T9	2		T12	1		T132	1
all_values[7]	auto[0]	auto[1]	auto[0]	151	1			T2	1		T9	3		T132	2
all_values[7]	auto[0]	auto[1]	auto[1]	98	1			T2	1		T9	1		T12	1
all_values[7]	auto[1]	auto[0]	auto[1]	197	1			T2	4		T9	3		T12	3
all_values[7]	auto[1]	auto[1]	auto[1]	197	1			T2	1		T9	4		T12	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal