Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	270713	1			T1	1		T2	1		T3	1
all_values[1]	270713	1			T1	1		T2	1		T3	1
all_values[2]	270713	1			T1	1		T2	1		T3	1
all_values[3]	270713	1			T1	1		T2	1		T3	1
all_values[4]	270713	1			T1	1		T2	1		T3	1
all_values[5]	270713	1			T1	1		T2	1		T3	1
all_values[6]	270713	1			T1	1		T2	1		T3	1
all_values[7]	270713	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2163442

1

T1

8

T2

8

T3

8

auto[1]

2262

1

T44

55

T45

116

T46

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2163593

1

T1

8

T2

8

T3

8

auto[1]

2111

1

T4

2

T15

10

T17

7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	270299	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	108	1			T45	8		T46	3		T361	3
all_values[0]	auto[1]	auto[0]	187	1			T44	6		T45	6		T46	6
all_values[0]	auto[1]	auto[1]	119	1			T45	6		T46	1		T361	11
all_values[1]	auto[0]	auto[0]	270309	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	116	1			T44	2		T45	7		T46	4
all_values[1]	auto[1]	auto[0]	178	1			T44	2		T45	5		T46	3
all_values[1]	auto[1]	auto[1]	110	1			T44	5		T45	9		T46	2
all_values[2]	auto[0]	auto[0]	270335	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	125	1			T44	5		T45	4		T46	2
all_values[2]	auto[1]	auto[0]	148	1			T44	2		T45	14		T46	5
all_values[2]	auto[1]	auto[1]	105	1			T44	3		T45	4		T46	3
all_values[3]	auto[0]	auto[0]	270301	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	133	1			T4	2		T120	4		T360	6
all_values[3]	auto[1]	auto[0]	159	1			T44	6		T45	8		T46	3
all_values[3]	auto[1]	auto[1]	120	1			T44	1		T45	5		T46	1
all_values[4]	auto[0]	auto[0]	270291	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	126	1			T14	3		T304	2		T358	1
all_values[4]	auto[1]	auto[0]	173	1			T44	4		T45	13		T46	3
all_values[4]	auto[1]	auto[1]	123	1			T44	4		T45	7		T46	2
all_values[5]	auto[0]	auto[0]	270042	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	369	1			T15	10		T17	7		T18	1
all_values[5]	auto[1]	auto[0]	208	1			T44	5		T45	4		T46	3
all_values[5]	auto[1]	auto[1]	94	1			T44	5		T45	7		T361	3
all_values[6]	auto[0]	auto[0]	270339	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	108	1			T44	5		T45	8		T46	3
all_values[6]	auto[1]	auto[0]	155	1			T44	2		T45	8		T46	5
all_values[6]	auto[1]	auto[1]	111	1			T44	2		T45	5		T46	2
all_values[7]	auto[0]	auto[0]	270327	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	114	1			T44	2		T45	1		T46	3
all_values[7]	auto[1]	auto[0]	142	1			T44	3		T45	5		T46	6
all_values[7]	auto[1]	auto[1]	130	1			T44	5		T45	10		T46	2