Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	30	54	64.29

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	28	20	41.67	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1200	1			T3	10		T8	4		T9	4
auto[SpiFlashAddrCfg]	1016	1			T3	4		T5	2		T11	13
auto[SpiFlashAddr3b]	1091	1			T3	4		T4	3		T5	2
auto[SpiFlashAddr4b]	883	1			T3	12		T4	4		T5	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3188

1

T4

7

T5

10

T8

4

auto[1]

1002

1

T3

30

T60

10

T70

14

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2243

1

T3

26

T4

4

T5

4

auto[1]

1947

1

T3

4

T4

3

T5

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1751	1			T3	10		T5	2		T8	4
values[1]	75	1			T194	2		T282	2		T256	4
values[2]	233	1			T3	8		T4	3		T58	4
values[3]	162	1			T5	2		T14	7		T94	4
values[4]	166	1			T11	4		T60	8		T158	3
values[5]	193	1			T10	4		T12	12		T58	3
values[6]	182	1			T11	8		T68	4		T92	4
values[7]	224	1			T3	12		T5	6		T52	4
values[8]	1204	1			T4	4		T11	7		T12	18

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3664

1

T3

30

T5

10

T8

4

auto[1]

526

1

T4

7

T10

7

T11

24

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

4066

1

T3

30

T4

7

T5

10

write

124

1

T68

16

T69

4

T51

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1817

1

T3

12

T4

3

T5

8

valids[0x1]

2373

1

T3

18

T4

4

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	190	1			T8	2		T52	2		T68	6
internal_process_ops[0x5a]	228	1			T52	4		T60	2		T70	4
internal_process_ops[0x05]	238	1			T8	2		T20	2		T70	2
internal_process_ops[0x35]	216	1			T3	6		T52	4		T20	2
internal_process_ops[0x15]	248	1			T3	4		T52	2		T119	8
internal_process_ops[0x03]	339	1			T4	4		T10	4		T11	5
internal_process_ops[0x0b]	338	1			T5	2		T10	3		T11	4
internal_process_ops[0x3b]	258	1			T11	7		T12	6		T20	2
internal_process_ops[0x6b]	194	1			T4	3		T5	2		T12	6
internal_process_ops[0xbb]	271	1			T11	7		T69	2		T94	2
internal_process_ops[0xeb]	296	1			T3	4		T5	6		T11	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4130

1

T3

30

T4

7

T5

10

auto[1]

60

1

T68

16

T71

2

T72

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4190

1

T3

30

T4

7

T5

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	28	20	41.67	28
Automatically Generated Cross Bins	48	28	20	41.67	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	*	*	*	--	--	16

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

928

1

T8

4

T9

4

T52

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

246

1

T3

10

T70

2

T68

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

552

1

T5

2

T12

6

T13

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

244

1

T3

4

T70

8

T68

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

644

1

T5

2

T12

14

T52

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

260

1

T3

4

T60

10

T70

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

474

1

T5

6

T12

10

T20

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

192

1

T3

12

T68

6

T94

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8

1

T278

2

T250

2

T249

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

16

1

T72

4

T83

2

T84

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

18

1

T74

2

T256

4

T265

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

8

1

T85

2

T86

2

T231

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

14

1

T252

4

T7

2

T299

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

14

1

T68

8

T85

2

T88

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

24

1

T69

4

T51

2

T207

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

22

1

T68

8

T71

2

T87

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

2

1

T300

2

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

194

1

T11

13

T14

6

T58

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

159

1

T4

3

T11

7

T14

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

171

1

T4

4

T10

7

T11

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	306	1			T9	4		T29	12		T26	6
auto[0]	values[0]	valids[0x1]	1368	1			T3	10		T5	2		T8	4
auto[0]	values[1]	valids[0x1]	70	1			T194	2		T282	2		T256	4
auto[0]	values[2]	valids[0x0]	118	1			T3	4		T184	2		T194	2
auto[0]	values[2]	valids[0x1]	80	1			T3	4		T180	12		T73	6
auto[0]	values[3]	valids[0x0]	82	1			T5	2		T186	2		T75	4
auto[0]	values[3]	valids[0x1]	44	1			T94	4		T171	2		T216	2
auto[0]	values[4]	valids[0x0]	112	1			T60	6		T69	2		T74	10
auto[0]	values[4]	valids[0x1]	22	1			T60	2		T272	2		T204	2
auto[0]	values[5]	valids[0x0]	84	1			T12	6		T70	2		T71	2
auto[0]	values[5]	valids[0x1]	68	1			T12	6		T68	2		T104	4
auto[0]	values[6]	valids[0x0]	90	1			T68	4		T92	4		T94	4
auto[0]	values[6]	valids[0x1]	56	1			T94	6		T51	2		T74	2
auto[0]	values[7]	valids[0x0]	122	1			T3	8		T5	6		T69	2
auto[0]	values[7]	valids[0x1]	68	1			T3	4		T52	4		T104	4
auto[0]	values[8]	valids[0x0]	588	1			T12	10		T13	2		T20	2
auto[0]	values[8]	valids[0x1]	386	1			T12	8		T70	4		T79	2
auto[1]	values[0]	valids[0x0]	6	1			T300	2		T301	4		-	-
auto[1]	values[0]	valids[0x1]	71	1			T10	3		T11	5		T14	8
auto[1]	values[1]	valids[0x1]	5	1			T302	5		-	-		-	-
auto[1]	values[2]	valids[0x0]	26	1			T4	3		T95	5		T303	7
auto[1]	values[2]	valids[0x1]	9	1			T58	4		T302	5		-	-
auto[1]	values[3]	valids[0x0]	25	1			T14	7		T95	3		T300	5
auto[1]	values[3]	valids[0x1]	11	1			T95	2		T304	6		T305	3
auto[1]	values[4]	valids[0x0]	20	1			T158	3		T120	1		T174	3
auto[1]	values[4]	valids[0x1]	12	1			T11	4		T91	2		T120	6
auto[1]	values[5]	valids[0x0]	25	1			T58	3		T91	5		T306	6
auto[1]	values[5]	valids[0x1]	16	1			T10	4		T307	5		T308	7
auto[1]	values[6]	valids[0x0]	30	1			T11	8		T95	4		T120	4
auto[1]	values[6]	valids[0x1]	6	1			T309	5		T310	1		-	-
auto[1]	values[7]	valids[0x0]	29	1			T311	5		T304	7		T312	5
auto[1]	values[7]	valids[0x1]	5	1			T95	3		T313	2		-	-
auto[1]	values[8]	valids[0x0]	154	1			T11	7		T58	3		T61	3
auto[1]	values[8]	valids[0x1]	76	1			T4	4		T58	7		T158	5