Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1807809 1 T3 1 T4 4380 T5 1696


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1615847 1 T3 1 T4 4380 T5 1696
auto[1] 191962 1 T8 4378 T50 518 T51 512


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 471577 1 T3 1 T4 1957 T5 315
auto[524288:1048575] 198666 1 T4 43 T5 331 T8 437
auto[1048576:1572863] 185217 1 T4 736 T8 5 T9 154
auto[1572864:2097151] 199403 1 T4 85 T8 1 T9 318
auto[2097152:2621439] 194899 1 T4 52 T8 479 T10 471
auto[2621440:3145727] 174720 1 T4 1113 T5 2 T9 322
auto[3145728:3670015] 209659 1 T4 285 T5 2 T8 506
auto[3670016:4194303] 173668 1 T4 109 T5 1046 T8 422


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 204796 1 T3 1 T4 38 T5 12
auto[1] 1603013 1 T4 4342 T5 1684 T8 2302


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1807809 1 T3 1 T4 4380 T5 1696


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 330198 1 T3 1 T4 1957 T5 315
auto[0] auto[0] auto[0:524287] auto[1] 141379 1 T8 4356 T50 256 T51 512
auto[0] auto[0] auto[524288:1048575] auto[0] 192696 1 T4 43 T5 331 T8 421
auto[0] auto[0] auto[524288:1048575] auto[1] 5970 1 T8 16 T50 1 T100 6
auto[0] auto[0] auto[1048576:1572863] auto[0] 178347 1 T4 736 T8 5 T9 154
auto[0] auto[0] auto[1048576:1572863] auto[1] 6870 1 T100 12 T180 509 T101 2891
auto[0] auto[0] auto[1572864:2097151] auto[0] 189257 1 T4 85 T8 1 T9 318
auto[0] auto[0] auto[1572864:2097151] auto[1] 10146 1 T100 141 T180 4467 T102 341
auto[0] auto[0] auto[2097152:2621439] auto[0] 188177 1 T4 52 T8 478 T10 471
auto[0] auto[0] auto[2097152:2621439] auto[1] 6722 1 T8 1 T50 4 T100 1
auto[0] auto[0] auto[2621440:3145727] auto[0] 170820 1 T4 1113 T5 2 T9 322
auto[0] auto[0] auto[2621440:3145727] auto[1] 3900 1 T50 257 T180 12 T181 1
auto[0] auto[0] auto[3145728:3670015] auto[0] 203045 1 T4 285 T5 2 T8 506
auto[0] auto[0] auto[3145728:3670015] auto[1] 6614 1 T100 1 T180 3 T101 2907
auto[0] auto[0] auto[3670016:4194303] auto[0] 163307 1 T4 109 T5 1046 T8 417
auto[0] auto[0] auto[3670016:4194303] auto[1] 10361 1 T8 5 T100 1481 T180 6389


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 204796 1 T3 1 T4 38 T5 12
auto[0] auto[0] auto[1] 1603013 1 T4 4342 T5 1684 T8 2302

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